Charge-retaining transistor, array of memory cells, and methods of forming a charge-retaining transistor

Patent metadata

Field	Value
Publication number	US-9159845-B2
Application number	US-201313894481-A
Country	US
Kind code	B2
Filing date	May 15, 2013
Priority date	May 15, 2013
Publication date	Oct 13, 2015
Grant date	Oct 13, 2015

Abstract

A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric. Islands of charge-trapping material are alongside the first semiconductor material. An oxidation-protective material is alongside the islands. Second semiconductor material is alongside the oxidation-protective material, and is of some different composition from that of the oxidation-protective material. Tunnel dielectric is alongside the charge-storage node. Channel material is alongside the tunnel dielectric. Additional embodiments, including methods, are disclosed.

First claim

The invention claimed is:

1. A vertically-oriented charge-retaining transistor comprising:
a control gate;
inter-gate dielectric extending vertically along a vertical sidewall of the control gate;
a charge-storage node comprising:
first semiconductor material extending vertically along a vertical sidewall of the inter-gate dielectric;
islands of charge-trapping material in a straight-line vertical cross section extending at least partially in a horizontally-oriented U-shape having a vertically-oriented base and two horizontally-oriented stems extending horizontally from the vertically-oriented base of the U-shape of the islands;
an oxidation-protective material extending vertically along the vertically-oriented base of the U-shape of the islands; and
second semiconductor material extending vertically along a vertical sidewall of the oxidation-protective material, and of some different composition from that of the oxidation-protective material;

tunnel dielectric extending vertically along the second semiconductor material; and
channel material extending vertically along a vertical sidewall of the tunnel dielectric, the two horizontally-oriented stems of the U-shape of the islands extending from the vertically-oriented base horizontally toward the channel material.

2. The transistor of claim 1 wherein the first semiconductor material is directly against the inter-gate dielectric.

3. The transistor of claim 1 wherein the charge-trapping material of the islands is directly against the first semiconductor material.

4. The transistor of claim 1 wherein the oxidation-protective material is directly against the charge-trapping material of the islands.

5. The transistor of claim 1 wherein the second semiconductor material is directly against the oxidation-protective material.

6. The transistor of claim 1 wherein the first and second semiconductor materials are of the same composition.

7. An array of elevationally extending strings of memory cells, individual of the memory cells comprising a charge-retaining transistor of claim 1 .

8. A vertically-oriented charge-retaining transistor comprising:
a control gate;
inter-gate dielectric extending vertically along a vertical sidewall of the control gate;
a charge-storage node comprising:
islands of charge-trapping material in a straight-line vertical cross section extending at least partially in a horizontally-oriented U-shape having a vertically-oriented base and two horizontally-oriented stems extending horizontally from the vertically-oriented base of the U-shape of the islands; and
semiconductor material extending vertically along the islands;

tunnel dielectric extending vertically along the semiconductor material of the charge-storage node; and
channel material extending vertically along a vertical sidewall of the tunnel dielectric, the two horizontally-oriented stems of the U-shape of the islands extending from the vertically-oriented base horizontally toward the channel material.

9. The transistor of claim 8 comprising semiconductive material laterally between the islands and the inter-gate dielectric.

10. An array of elevationally extending strings of memory cells, individual of the memory cells comprising a charge-retaining transistor of claim 8 .

11. An array of elevationally extending strings of memory cells, the strings individually comprising:
an active area pillar extending elevationally through alternating tiers of inter-tier dielectric material and transistor material, the transistor material comprising:
a control gate;
inter-gate dielectric extending vertically along a vertical sidewall of the control gate;
a charge-storage node comprising:
islands of charge-trapping material in a straight-line vertical cross section extending at least partially in a horizontally-oriented U-shape having a vertically-oriented base and two horizontally-oriented stems extending horizontally from the vertically-oriented base of the U-shape of the islands; and
an oxidation-protective material extending vertically along the vertically-oriented base of the U-shape of the islands; and

tunnel dielectric extending vertically laterally between the charge-storage node and the active area pillar; and

the oxidation-protective material extending vertically along a vertical sidewall of the active area pillar between the active area pillar and the inter-tier dielectric.

12. The array of claim 11 wherein the charge-storage node comprises:
first semiconductor material extending vertically laterally between the inter-gate dielectric and the islands; and
second semiconductor material extending vertically laterally between the oxidation-protective material and the tunnel dielectric, the second semiconductor material being of some different composition from that of the oxidation-protective material.

13. The transistor of claim 1 wherein the oxidation-protective material comprises RuO 2 .

14. The transistor of claim 1 wherein the oxidation-protective material comprises silicon nitride.

15. The transistor of claim 1 wherein the oxidation-protective material comprises HfO x .

16. The transistor of claim 1 wherein the oxidation-protective material is amorphous.

17. The transistor of claim 1 wherein the oxidation-protective material is crystalline.

18. The transistor of claim 1 wherein the inter-gate dielectric in the straight-line vertical cross section is at least partially extending in a horizontally-oriented U-shape having a vertically-oriented base and two horizontally-oriented stems extending horizontally from the vertically-oriented base of the U-shape of the inter-gate dielectric.

19. The transistor of claim 1 wherein the first semiconductor material in the straight-line vertical cross section is at least partially extending in a horizontally-oriented U-shape having a vertically-oriented base and two horizontally-oriented stems extending horizontally from the vertically-oriented base of the U-shape of the first semiconductor material.

20. The transistor of claim 1 wherein the oxidation-protective material in the straight-line vertical cross section is at least partially extending in a horizontally-oriented U-shape having a vertically-oriented base and two horizontally-oriented stems extending horizontally from the vertically-oriented base of the U-shape of the oxidation-protective material.

21. The transistor of claim 1 wherein no portion of the second semiconductor material has a U-shape in the vertical cross section.

22. The transistor of claim 1 wherein no portion of the tunnel dielectric has a U-shape in the vertical cross section.

23. The transistor of claim 8 wherein the inter-gate dielectric in the straight-line vertical cross section is at least partially extending in a horizontally-oriented U-shape having a vertically-oriented base and two horizontally-oriented stems extending horizontally from the vertically-oriented base of the U-shape of the inter-gate dielectric.

24. The transistor of claim 9 wherein the semiconductor material laterally between the islands and the inter-gate dielectric in the straight-line vertical cross section is at least partially extending in a horizontally-oriented U-shape having a vertically-oriented base and two horizontally-oriented stems extending horizontally from the vertically-oriented base of the U-shape of the semiconductor material.

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy D V Nirmal

Classifications

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D30/6893 Primary

  wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate · CPC title

• H10D30/697

  having trapping at multiple separated sites, e.g. multi-particles trapping sites · CPC title