Gate Structure and Method for Fabricating the Same
US-2015372149-A1 · Dec 24, 2015 · US
NAND string containing self-aligned control gate sidewall cladding
US8969153B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969153-B2 |
| Application number | US-201313932060-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 1, 2013 |
| Priority date | Jul 1, 2013 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
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A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates.
First claim
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What is claimed is: 1. A method of making a NAND string, comprising: forming a tunnel dielectric over a semiconductor channel; forming a charge storage layer over the tunnel dielectric; forming a blocking dielectric over the charge storage layer; forming a control gate layer over the blocking dielectric; patterning the control gate layer to form a plurality of control gates separated by trenches, wherein the step of patterning the control gate layer comprises a first etchi…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H10D30/6891Primary
Electricity · mapped topic
- H01L21/28273Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8969153B2 cover?
- A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenc…
- Who is the assignee on this patent?
- Sandisk Technologies Inc, Sandisk Technologies Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6891. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).