3DIC stacking device and method of manufacture

Patent metadata

Field	Value
Publication number	US-10109613-B2
Application number	US-201615262788-A
Country	US
Kind code	B2
Filing date	Sep 12, 2016
Priority date	Jun 27, 2012
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor die encapsulated by a first encapsulant;
at least one through substrate via extending through at least a portion of the first semiconductor die and being exposed on a first side of the first semiconductor die;
first external connectors located on a second side of the first semiconductor die, the first external connectors being planar with the first encapsulant;
a first redistribution layer in electrical connection with the first external connectors, the first redistribution layer extending over the first encapsulant; and
a second semiconductor die in electrical connection with the at least one through substrate via, the second semiconductor die extending over the first encapsulant, wherein the second semiconductor die and the first redistribution layer are located on a same side of the first encapsulant, wherein the second semiconductor die is offset from the first semiconductor die.

2. The semiconductor device of claim 1 , further comprising;
a third semiconductor die encapsulated by the first encapsulant; and
a fourth semiconductor die in electrical connection with the third semiconductor die, the fourth semiconductor die extending over the first encapsulant.

3. The semiconductor device of claim 2 , wherein the second semiconductor die and the fourth semiconductor die are encapsulated by a second encapsulant.

4. The semiconductor device of claim 1 , further comprising a second redistribution layer in electrical connection with the at least one through substrate via, the second redistribution layer extending over the first encapsulant.

5. The semiconductor device of claim 1 , wherein the offset is between about 100 um and about 3 mm.

6. The semiconductor device of claim 5 , wherein the offset is between about 100 um and about 1.5 mm.

7. The semiconductor device of claim 1 , wherein the second semiconductor die has a width of between about 3 mm and about 14 mm.

8. A semiconductor device comprising:
two or more bottom dies;
a first molding compound between the two or more bottom dies, the first molding compound in physical contact with first electrical contacts on the two or more bottom dies and wherein the first electrical contacts are exposed;
through vias extending through the two or more bottom dies, the through vias being exposed through the two or more bottom dies on an opposite side of the two or more bottom dies than the exposed first electrical contacts side, wherein a first line extends from the exposed first electrical contacts side to the opposite side and wherein a line perpendicular with the first line intersects with each of the two or more bottom dies and the first molding compound;
second electrical contacts in electrical connection to the through vias along a backside of the two or more bottom dies;
two or more top dies attached to the two or more bottom dies, wherein the two or more top dies are each directly electrically connected to a first redistribution layer; and
a first set of external connections, wherein each of the first set of external connections is physically in contact with one of the second electrical contacts, wherein one of the two or more top dies overlies and is offset from one of the two or more bottom dies by between about 100 μm and about 3 mm.

9. The semiconductor device of claim 8 , wherein the one of the two or more top dies has a larger width than the one of the two or more bottom dies.

10. The semiconductor device of claim 9 , wherein the one of the two or more top dies has a width of between about 3 mm and about 14 mm.

11. The semiconductor device of claim 8 , further comprising an encapsulant encapsulating two of the two or more top dies.

12. The semiconductor device of claim 8 , wherein the first set of external connections is a solder ball.

13. The semiconductor device of claim 8 , further comprising a printed circuit board in physical contact with the first set of external connections.

14. The semiconductor device of claim 8 , wherein the offset is between about 100 μm and about 1.5 mm.

15. A semiconductor device comprising:
a first semiconductor die comprising first external contacts, wherein a surface of the first external contacts is at least partially covered by a polymer material, the polymer material having a first sidewall that is planar with a second sidewall of the first semiconductor die;
a second semiconductor die laterally removed from the first semiconductor die, the second semiconductor die comprising second external contacts;
an encapsulant encapsulating the first semiconductor die and the second semiconductor die, the encapsulant being different from the polymer material, wherein the encapsulant is a single material, wherein a first surface of the first external contacts and a second surface of the second external contacts are exposed, wherein the encapsulant, the first external contacts, and the second external contacts are planar with each other along a first surface, the first semiconductor die, the second semiconductor die, and the encapsulant each being on a first side of the first surface;
first through substrate vias in the first semiconductor die and second through substrate vias in the second semiconductor die; and
a third semiconductor die electrically connected to the first through substrate vias and a fourth semiconductor die electrically connected to the second through substrate vias, wherein the third semiconductor die has a first width of between about 1 mm and about 20 mm, the first semiconductor die has a second width of between about 3 mm and about 14 mm, and wherein the second width is less than the first width.

16. The semiconductor device of claim 15 , further comprising an external connection in physical contact with one of the first external contacts.

17. The semiconductor device of claim 16 , wherein the external connection is a solder ball.

18. The semiconductor device of claim 15 , further comprising a redistribution layer between the third semiconductor die and the first semiconductor die.

19. The semiconductor device of claim 18 , wherein the redistribution layer is the only redistribution layer adjacent to the encapsulant.

20. The semiconductor device of claim 15 , wherein the fourth semiconductor die is wider than the second semiconductor die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jing-Cheng
• Yu Chen-Hua

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title