Packages with through-vias having tapered ends

Patent metadata

Field	Value
Publication number	US-9735134-B2
Application number	US-201414206248-A
Country	US
Kind code	B2
Filing date	Mar 12, 2014
Priority date	Mar 12, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A package includes a device die, a molding material molding the device die therein, a through-via substantially penetrating through the molding material, wherein the through-via has an end. The end of the through-via is tapered and has rounded sidewall surfaces. The package further includes a redistribution line electrically coupled to the through-via.

First claim

What is claimed is:

1. A package comprising:
a device die;
a molding material molding the device die therein;
a conductive through-via substantially penetrating through the molding material, wherein the conductive through-via comprises:
a first end, and wherein the first end is tapered and comprises rounded sidewall surfaces; and
a second end opposite to the first end, wherein the second end has substantially straight edges, and the first end is narrower than the second end; and
a redistribution line electrically coupled to the conductive through-via.

2. The package of claim 1 further comprising:
a dielectric layer on a side of the molding material; and
a conductive via penetrating through the dielectric layer, wherein the conductive via interconnects the conductive through-via and the redistribution line, and wherein the conductive via is in contact with both the conductive through-via and the redistribution line.

3. The package of claim 2 , wherein an interface between the conductive via and the metal post conductive through-via is rounded.

4. The package of claim 2 , wherein the dielectric layer comprises a portion extending into the molding material, and wherein the conductive via extends into the portion of the dielectric layer.

5. The package of claim 2 , wherein the conductive via further comprises a portion extending into the molding material, and wherein sidewalls of an entirety of the portion of the conductive via are in contact with the molding material.

6. The package of claim 2 , wherein the conductive via is in contact with a planar surface of the conductive through-via.

7. A package comprising:
at least one first dielectric layer;
a first plurality of redistribution lines in the at least one first dielectric layer;
a device die over and electrically coupled to the first plurality of redistribution lines;
a molding material molding the device die therein;
a conductive through-via in the molding material, wherein a top end portion of the conductive through-via comprises rounded sidewalls, and the top end portion of the conductive through-via comprises a rounded top surface lower than a top surface of the molding material;
at least one second dielectric layer over the device die; and
a second plurality of redistribution lines in the at least one second dielectric layer, wherein one of the second plurality of redistribution lines is electrically coupled to one of the first plurality of redistribution lines through the conductive through-via.

8. The package of claim 7 further comprising:
a dielectric layer over the molding material; and
a conductive via penetrating through the dielectric layer, wherein the conductive via comprises a bottom in contact with the top end portion of the conductive through-via.

9. The package of claim 8 , wherein the dielectric layer comprises a portion extending into the molding material, and wherein the conductive via further extends into the portion of the dielectric layer.

10. The package of claim 8 , wherein the conductive via further comprises a portion extending into the molding material, and wherein sidewalls of an entirety of the portion of the conductive via are in contact with the molding material.

11. The package of claim 7 further comprising:
a plurality of solder regions underlying and electrically coupled to the first plurality of redistribution lines, wherein the plurality of solder regions bonds the package to a Printed Circuit Board (PCB).

12. A package comprising:
a conductive through-via comprising:
a first portion having first sidewalls, wherein the first sidewalls are substantially vertical and straight; and
a second portion having second sidewalls continuously connected to the first sidewalls, wherein the second sidewalls are rounded and tapered;

an encapsulating material encapsulating the conductive through-via therein, wherein a first surface of the encapsulating material is coplanar with a second surface of the second portion of the conductive through-via;
a dielectric layer contacting the encapsulating material; and
a redistribution line comprising a conductive via extending into the dielectric layer, wherein the via has a surface contacting the second surface of the second portion of the conductive through-via; and
a device die encapsulated in the encapsulating material, wherein the device die comprises metal pillars having top surfaces coplanar with the first surface.

13. The package of claim 12 , wherein the second surface and the surface of the conductive via form a planar interface.

14. The package of claim 13 , wherein the planar interface has a first dimension smaller than a second dimension of the first portion of the conductive through-via, with both the first dimension and the second dimension being measured in planes perpendicular to the first sidewalls.

15. The package of claim 12 , wherein the first portion of the conductive through-via has an end portion having sidewalls substantially perpendicular to an interface between the dielectric layer and the encapsulating material.

16. The package of claim 12 , wherein an entirety of the conductive through-via is in the encapsulating material.

17. The package of claim 1 , wherein the substantially straight edges extend to a majority of the conductive through-via, and the rounded sidewall surfaces of the first end taper starting from the substantially straight edges.

18. The package of claim 7 , wherein the conductive through-via further comprises a middle portion and a bottom portion having substantially straight edges.

19. The package of claim 18 , wherein the middle portion and the bottom portion of the conductive through-via are narrower than the top end portion of the conductive through-via.

20. The package of claim 12 , wherein the first portion of the conductive through-via are wider than the second portion of the conductive through-via.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hsien-Wei

Classifications

• H10P72/7448

  the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title