Pop structures and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9490167-B2
Application number	US-201514618446-A
Country	US
Kind code	B2
Filing date	Feb 10, 2015
Priority date	Oct 11, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a Through Assembly Via (TAV) penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line.

First claim

What is claimed is:

1. A method comprising:
bonding a discrete passive device to a package, wherein the package comprises:
a first molding material;
a first device die molded in the first molding material, wherein the first device die comprises metal posts;
a Through Assembly Via (TAV) penetrating through the first molding material; and
a first redistribution line over the first molding material; and

molding the discrete passive device in a second molding material, wherein the discrete passive device is bonded directly to the package, and an entirety of the discrete passive device is embedded in and surrounded by the second molding material.

2. The method of claim 1 , wherein after the bonding, the discrete passive device is electrically coupled to the first redistribution line and the TAV.

3. The method of claim 1 further comprising, before the molding, bonding a second device die to the package, with the second device die molded in the second molding material.

4. The method of claim 3 , wherein the second device die is bonded directly to the package.

5. The method of claim 1 , wherein a top surface of the second molding material is higher than a top surface of the discrete passive device.

6. The method of claim 1 , wherein the first redistribution line is in a dielectric layer, and edges of the dielectric layer are aligned with respective edges of the second molding material.

7. A method comprising:
bonding a first device die directly to a package, wherein the package comprises:
a first molding material, the first molding material comprising a first topmost surface and a first bottommost surface;
a second device die molded in the first molding material;
a Through Assembly Via (TAV) penetrating through the first molding material, the TAV comprising a second topmost surface and a second bottommost surface, wherein the second topmost surface is coplanar with the first topmost surface, and the second bottommost surface is coplanar with the first bottommost surface; and
a plurality of redistribution lines over the first molding material and electrically coupled to the second device die and the TAV; and

molding the first device die in a second molding material.

8. The method of claim 7 , wherein after the bonding, the first device die is electrically coupled to the plurality of redistribution lines.

9. The method of claim 7 further comprising, before the molding, bonding a discrete passive device to the package, with the discrete passive device molded in the second molding material.

10. The method of claim 9 , wherein the discrete passive device is bonded directly to the package.

11. The method of claim 7 further comprising forming the package comprising:
pre-forming the TAV; and
placing the TAV and the second device die over a carrier.

12. The method of claim 7 further comprising forming the package comprising:
performing a plating to form the TAV over a carrier; and
placing the second device die over the carrier.

13. The method of claim 7 , wherein a top surface of the second molding material is higher than a top surface of the first device die.

14. The method of claim 7 , wherein an entirety of the first device die is encapsulated in the second molding material.

15. The method of claim 7 , wherein the plurality of redistribution lines are formed in a plurality of dielectric layers, and edges of the plurality of dielectric layers are aligned with respective edges of the second molding material.

16. A method comprising:
bonding a discrete passive device to a package, wherein the package comprises:
a first molding material;
a first device die molded in the first molding material, wherein the first device die comprises metal posts, the first device die comprising a first surface and a second surface opposite the first surface, the metal posts comprising third surfaces and fourth surfaces opposite the third surfaces, wherein the first surface is coplanar with a topmost surface of the first molding material, the third surfaces physically contact the second surface, and the fourth surfaces are coplanar with a bottommost surface of the first molding material;
a Through Assembly Via (TAV) penetrating through the first molding material; and
a first redistribution line over the first molding material;

bonding a second device die to the package; and
molding the discrete passive device and the second device die in a second molding material.

17. The method of claim 16 , wherein after the bonding, the discrete passive device is electrically coupled to the first redistribution line and the TAV.

18. The method of claim 16 , wherein the discrete passive device is bonded directly to the package, and an entirety of the discrete passive device is embedded in the second molding material.

19. The method of claim 16 , wherein the second device die is bonded directly to the package.

20. The method of claim 16 , wherein a top surface of the second molding material is higher than a top surface of the discrete passive device.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Manufactoring Company Ltd

Inventors

• Chen Hsu-Hsien
• Chen Chih-Hua
• Yeh En-Hsiang
• Liu Monsen
• Chen Chen-Shien

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/874

  On different surfaces · CPC title