Process for forming package-on-package structures

Patent metadata

Field	Value
Publication number	US-9666572-B2
Application number	US-201615186757-A
Country	US
Kind code	B2
Filing date	Jun 20, 2016
Priority date	Oct 17, 2011
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.

First claim

What is claimed is:

1. A method comprising:
forming a first plurality of redistribution lines;
forming metal posts over and electrically coupled to the first plurality of redistribution lines;
attaching a back surface of a first device die to one of the first plurality of redistribution lines through a die-attach film, wherein the die-attach film contacts the one of the first plurality of redistribution lines;
encapsulating the first device die and the metal posts in an encapsulation material, wherein the die-attach film is encapsulated in the encapsulating material, with sidewalls of the die-attach film being in contact with the encapsulating material; and
forming a second plurality of redistribution lines electrically coupling to the first device die, wherein the first plurality of redistribution lines and the second plurality of redistribution lines are on opposite sides of the metal posts.

2. The method of claim 1 , wherein top surfaces of the metal posts are coplanar with a top surface of the encapsulation material, and bottom surfaces of the metal posts are in contact with top surfaces of the first plurality of redistribution lines.

3. The method of claim 1 , wherein the metal posts are formed as protruding over top surfaces of the first plurality of redistribution lines.

4. The method of claim 1 further comprising, after the encapsulating, performing a lithography process on the encapsulation material to expose the metal posts and electrical connectors of the first device die.

5. The method of claim 1 further comprising, after the encapsulating, grinding the encapsulation material to expose the metal posts.

6. The method of claim 5 , wherein after the grinding, electrical connectors of the first device die are covered by dielectric regions, and the method further comprises, removing the dielectric regions to form openings in the encapsulating material, wherein the electrical connectors of the first device die are exposed to the openings.

7. The method of claim 1 further comprising bonding a second device die onto the first plurality of redistribution lines.

8. The method of claim 7 , wherein a solder region bonds the second device die to the one of the first plurality of redistribution lines.

9. A method comprising:
forming a dielectric layer;
patterning the dielectric layer to form openings;
forming a first plurality of redistribution lines, wherein the first plurality of redistribution lines comprises first portions extending into the openings, and second portions over the dielectric layer;
forming metal posts over and electrically connected to some of the first plurality of redistribution lines, wherein one of the metal posts is formed on the second portion of one of the first plurality of redistribution lines;
attaching a first device die to the first portion of the one of the first plurality of redistribution lines;
encapsulating the metal posts and the first device die in an encapsulating material; and
grinding the encapsulating material, wherein metal posts and electrical connectors of the first device die are exposed.

10. The method of claim 9 further comprising bonding a second device die to the one of the first plurality of redistribution lines.

11. The method of claim 10 , wherein a solder region is in contact with both the second device die and the first portion of the one of the first plurality of redistribution lines.

12. The method of claim 11 , wherein the first device die is attached to the first portion of the one of the first plurality of redistribution lines through a die-attach film, and the die-attach film and the solder region are in physical contact with opposite surfaces of the first portion of the one of the first plurality of redistribution lines.

13. The method of claim 9 , wherein the metal posts are exposed by the grinding.

14. The method of claim 9 , wherein the electrical connectors of the first device die are exposed by removing dielectric regions covering the electrical connectors.

15. A method comprising:
forming a first redistribution line;
forming a metal post over a first end portion of the first redistribution line, wherein the metal post is formed by plating starting from the first redistribution line;
attaching a first device die to a second end portion of the first redistribution line;
encapsulating the metal post and the first device die in an encapsulation material;
removing dielectric regions covering electrical connectors of the first device die to expose the electrical connectors;
forming a second plurality of redistribution lines over and electrically coupling to the first redistribution line and the metal post, wherein the second plurality of redistribution lines is further electrically connected to the electrical connectors; and
bonding a second device die to the first redistribution line, wherein the first device die is attached to a first side of the first redistribution line through a die-attach film, and the second device die is bonded to the first redistribution line through a solder region.

16. The method of claim 15 further comprising grinding the encapsulation material to expose the metal post.

17. The method of claim 16 , wherein after the grinding, the metal post is exposed.

18. The method of claim 15 , wherein the second plurality of redistribution lines extends into openings formed by the removed dielectric regions to contact the electrical connectors of the first device die.

19. The method of claim 15 , wherein the metal post is formed by plating starting from the first redistribution line.

20. The method of claim 1 , wherein the metal posts are formed by plating starting from the first plurality of redistribution lines.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chih-Wei
• Cheng Ming-Da
• Chen Meng-Tse
• Lu Wen-Hsiung
• Huang Kuei-Wei
• Liu Chung-Shi

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title