Semiconductor package and method for fabricating a semiconductor package

Patent metadata

Field	Value
Publication number	US-10490470-B2
Application number	US-201715838417-A
Country	US
Kind code	B2
Filing date	Dec 12, 2017
Priority date	Dec 13, 2016
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

A method of fabricating a semiconductor package comprises providing a carrier, fabricating an opening in the carrier, attaching a semiconductor chip to the carrier and fabricating an encapsulation body covering the semiconductor chip.

First claim

The invention claimed is:

1. A method of fabricating a semiconductor package, the method comprising:
providing a carrier;
fabricating an opening in the carrier;
attaching a semiconductor chip to the carrier; and
fabricating an encapsulation body covering the semiconductor chip;
applying a paste onto the carrier prior to fabricating the opening and prior to fabricating the encapsulation body, wherein the paste is applied at a designated position of the opening.

2. The method of claim 1 , wherein the opening is configured to relieve the semiconductor package from stress.

3. The method of claim 2 , wherein the stress is based on a difference between the coefficients of thermal expansion of the carrier and the semiconductor chip.

4. The method of claim 1 , wherein the fabricating of the opening in the carrier comprises at least one of cutting and drilling through the carrier.

5. The method of claim 4 , wherein the at least one of cutting and drilling is performed using a laser.

6. The method of one claim 1 , further comprising:
attaching the carrier to a temporary carrier prior to fabricating the opening.

7. The method of claim 1 , wherein the opening comprises a hole or a trench.

8. The method of claim 1 , wherein the opening comprises a trench that separates the carrier into a first segment and a second segment.

9. The method of claim 8 , further comprising:
attaching the carrier to a temporary carrier prior to fabricating the trench, wherein the temporary carrier is configured to keep the first segment and the second segment in a defined position relative to each other.

10. The method of claim 8 , further comprising:
applying the paste onto the carrier prior to fabricating the trench, the paste being configured to keep the first and second segments in a defined position relative to each other.

11. The method of claim 1 , wherein the semiconductor chip comprises a photo active area and wherein the opening is configured to let light pass between the photo active area and the outside of the semiconductor package.

Assignees

• Infineon Technologies Ag

Inventors

• Chong Hock Heng
• Chan Sook Woon
• Chiang Chau Fatt
• Chung Khar Foong
• Fang Chee Hong
• Muhammad Muhammat Sanusi
• Ng Mei Chin
• Ng Yean Seng
• Pok Pei Luan
• Wang Choon Huey

Classifications

• H10W74/00 Primary

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/072

  of bump connectors · CPC title