Semiconductor package and method for fabricating a semiconductor package

Patent metadata

Field	Value
Publication number	US-2018174935-A1
Application number	US-201715838417-A
Country	US
Kind code	A1
Filing date	Dec 12, 2017
Priority date	Dec 13, 2016
Publication date	Jun 21, 2018
Grant date	—

Abstract

A method of fabricating a semiconductor package comprises providing a carrier, fabricating an opening in the carrier, attaching a semiconductor chip to the carrier and fabricating an encapsulation body covering the semiconductor chip.

First claim

1 . A method of fabricating a semiconductor package, the method comprising:
providing a carrier; fabricating an opening in the carrier; attaching a semiconductor chip to the carrier; and fabricating an encapsulation body covering the semiconductor chip.

2 . The method of claim 1 , wherein the opening is configured to relieve the semiconductor package from stress.

3 . The method of claim 2 , wherein the stress is based on a difference between the coefficients of thermal expansion of the carrier and the semiconductor chip.

4 . The method of claim 1 , wherein the fabricating of the opening in the carrier comprises at least one of cutting and drilling through the carrier.

5 . The method of claim 4 , wherein the at least one of cutting and drilling is performed using a laser.

6 . The method of one claim 1 , further comprising:
attaching the carrier to a temporary carrier prior to fabricating the opening.

7 . The method of claim 1 , further comprising:
applying a paste onto the carrier prior to fabricating the opening, wherein the paste is applied at the designated position of the opening.

8 . The method of claim 1 , wherein the opening comprises a hole or a trench.

9 . The method of claim 1 , wherein the opening comprises a trench that separates the carrier into a first segment and a second segment.

10 . The method of claim 9 , further comprising:
attaching the carrier to a temporary carrier prior to fabricating the trench, wherein the temporary carrier is configured to keep the first segment and the second segment in a defined position relative to each other.

11 . The method of claim 9 , further comprising:
applying a paste onto the carrier prior to fabricating the trench, the paste being configured to keep the first and second segments in a defined position relative to each other.

12 . The method of claim 1 , wherein the semiconductor chip comprises a photo active area and wherein the opening is configured to let light pass between the photo active area and the outside of the semiconductor package.

13 . A semiconductor package, comprising:
a carrier comprising an opening; a semiconductor chip attached to the carrier; and an encapsulation body covering the semiconductor chip, wherein the opening is configured to relieve the semiconductor package from stress.

14 . The semiconductor package of claim 13 , wherein the carrier comprises one or more of a leadframe, a laminate, an epoxy, an epoxy mold compound, a thermoset plastic, or a fiber-reinforced plastic.

15 . The semiconductor package of claim 13 , wherein the opening is at least partially filled with the encapsulation body.

16 . The semiconductor package of claim 13 , wherein the opening is at least partially filled with a paste of dielectric material that is different from the material of the encapsulation body.

17 . The semiconductor package of claim 16 , wherein the paste comprises a polymer.

18 . The semiconductor package of claim 17 , wherein the polymer comprises silicone.

19 . An optoelectronic semiconductor package, comprising:
a carrier comprising an opening; a semiconductor chip comprising a photo active area and attached to the carrier, wherein the photo active area faces the opening; an optically transparent paste arranged in the opening; and an encapsulation body covering the semiconductor chip, wherein the optically transparent paste comprises a material that is different from the encapsulation body.

20 . The optoelectronic semiconductor package of claim 19 , wherein the carrier comprises one or more of a leadframe, a laminate, an epoxy, an epoxy mold compound, a thermoset plastic, or a fiber-reinforced plastic.

Assignees

• Infineon Technologies Ag

Inventors

• Chong Hock Heng
• Chan Sook Woon
• Chiang Chau Fatt
• Chung Khar Foong
• Fang Chee Hong
• Muhammad Muhammat Sanusi
• Ng Mei Chin
• Ng Yean Seng
• Pok Pei Luan
• Wang Choon Huey

Classifications

• H10W74/00 Primary

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/072

  of bump connectors · CPC title