Methods of forming merged source/drain regions on integrated circuit products

Patent metadata

Field	Value
Publication number	US-10475904-B2
Application number	US-201815868004-A
Country	US
Kind code	B2
Filing date	Jan 11, 2018
Priority date	Jan 11, 2018
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess. In this particular example, the method also includes removing a first substantially horizontally-oriented portion of the P-type-doped semiconductor material from within the recess while leaving a second substantially horizontally-oriented portion of the P-type-doped semiconductor material remaining in the recess and forming a substantially horizontally-oriented N-type-doped semiconductor material in the recess laterally adjacent the second substantially horizontally-oriented portion of the P-type-doped semiconductor material, wherein the substantially horizontally-oriented N-type-doped semiconductor material physically engages the second substantially horizontally-oriented portion of the P-type-doped semiconductor material along an interface within the merged source/drain region.

First claim

What is claimed is:

1. A method of forming a merged source/drain region, comprising:
forming first and second vertically oriented channel semiconductor (VOCS) structures above a semiconductor substrate;
forming a recess in said substrate between said first and second VOCS structures;
forming a substantially horizontally-oriented P-type-doped semiconductor material in said recess;
removing a first substantially horizontally-oriented portion of said substantially horizontally-oriented P-type-doped semiconductor material from within said recess while leaving a second substantially horizontally-oriented portion of said P-type-doped semiconductor material remaining in said recess; and
forming a substantially horizontally-oriented N-type-doped semiconductor material in said recess laterally adjacent said second substantially horizontally-oriented portion of said P-type-doped semiconductor material, wherein said substantially horizontally-oriented N-type-doped semiconductor material physically engages said second substantially horizontally-oriented portion of said P-type-doped semiconductor material along an interface within said merged source/drain region.

2. The method of claim 1 , further comprising, prior to removing said first substantially horizontally-oriented portion of said P-type-doped semiconductor material, forming a patterned etch mask above said P-type-doped semiconductor material that covers said second substantially horizontally-oriented portion of said P-type-doped semiconductor material and exposes at least a portion of said first substantially horizontally-oriented portion of said P-type-doped semiconductor material.

3. The method of claim 2 , wherein removing said first substantially horizontally-oriented portion of said P-type-doped semiconductor material comprises performing an anisotropic etching process, with said patterned etch mask covering said second substantially horizontally-oriented portion of said P-type-doped semiconductor material, to remove said first substantially horizontally-oriented portion of said P-type-doped semiconductor material.

4. The method of claim 3 , wherein removing said first substantially horizontally-oriented portion of said P-type-doped semiconductor material further comprises, after performing said anisotropic etching process, performing an isotropic etching process, with said patterned etch mask covering said second substantially horizontally-oriented portion of said P-type-doped semiconductor material, to remove said first substantially horizontally-oriented portion of said P-type-doped semiconductor material.

5. The method of claim 1 , wherein forming said substantially horizontally-oriented P-type-doped semiconductor material in said recess comprises performing an epitaxial growth process while introducing a P-type dopant during said epitaxial growth process so as to form a substantially horizontally-oriented in situ P-type-doped semiconductor material in said recess.

6. The method of claim 1 , wherein forming said substantially horizontally-oriented P-type-doped semiconductor material in said recess comprises:
performing an epitaxial growth process to form an undoped substantially horizontally-oriented semiconductor material in said recess; and
performing an ion implantation process to introduce a P-type dopant into said undoped substantially horizontally-oriented semiconductor material in said recess, thereby forming said P-type-doped semiconductor material.

7. The method of claim 1 , wherein forming said substantially horizontally-oriented N-type-doped semiconductor material in said recess comprises performing an epitaxial growth process while introducing an N-type dopant during said epitaxial growth process so as to form a substantially horizontally-oriented in situ N-type-doped semiconductor material in said recess.

8. The method of claim 1 , wherein said interface between said second substantially horizontally-oriented portion of P-type-doped semiconductor material and said substantially horizontally-oriented N-type-doped semiconductor material is a substantially vertically oriented interface.

9. The method of claim 1 , further comprising:
forming additional components of a P-type vertical transistor around said first VOCS structure; and
forming additional components of an N-type vertical transistor around said second VOCS structure, wherein said P-type vertical transistor and said N-type vertical transistor are connected to each other by said merged source/drain region.

10. The method of claim 1 , wherein said merged source/drain region is a part of an SRAM (Static Random Access Memory) cell.

11. The method of claim 1 , wherein said substantially horizontally-oriented P-type-doped semiconductor material comprises one of boron (B), boron difluoride (BF2), and gallium (Ga) and said N-type-doped semiconductor material comprises one of phosphorous and arsenic.

12. The method of claim 1 , wherein said substantially horizontally-oriented P-type-doped semiconductor material comprises silicon germanium (SiGe) having a germanium concentration of about 30-60% (atomic percent) and said substantially horizontally-oriented N-type-doped semiconductor material comprises one of phosphorous doped silicon and arsenic doped silicon.

13. A method of forming a merged source/drain region, comprising:
forming first and second vertically oriented channel semiconductor (VOCS) structures above a semiconductor substrate;
performing at least an anisotropic etching process to form a recess in said substrate between said first and second VOCS structures;
performing a first epitaxial growth process while introducing a P-type dopant during said first epitaxial growth process so as to form a substantially horizontally-oriented in situ P-type-doped semiconductor material in said recess;
removing a first substantially horizontally-oriented portion of said substantially horizontally-oriented in situ P-type-doped semiconductor material from within said recess while leaving a second substantially horizontally-oriented portion of said substantially horizontally-oriented in situ P-type-doped semiconductor material remaining in said recess; and
performing a second epitaxial growth process while introducing an N-type dopant during said second epitaxial growth process so as to form a substantially horizontally-oriented in situ N-type-doped semiconductor material in said recess adjacent said second substantially horizontally-oriented portion of said substantially horizontally-oriented in situ P-type-doped semiconductor material, wherein said substantially horizontally-oriented in situ N-type-doped semiconductor material physically engages said second substantially horizontally-oriented portion of said substantially horizontally-oriented in situ P-type-doped semiconductor material along an interface within said merged source/drain region.

14. The method of claim 13 , further comprising, prior to removing said first substantially horizontally-oriented portion of said substantially horizontally-oriented in situ P-type-doped semiconductor material, forming a patterned etch mask above said substantially horizontally-oriented in situ P-type-doped semiconductor material that covers said second substantially horizontally-oriented portion of said substantially horizontally-oriented in situ P-type-doped semiconductor material and exposes at least a portion of said first substantially horizontally-oriented portion of said substantially horizontally-oriented in situ P-type-doped semiconductor material.

15. The method of claim 14 , wherein removing said first substantially horizontally-oriented portion of said su

Assignees

• Globalfoundries Inc

Inventors

• Niimi Hiroaki
• Bentley Steven
• Lallement Romain
• Anderson Brent A
• Wang Junli
• Sankarapandian Muthumanickam

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L27/1104

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic

• H01L27/092

  Electricity · mapped topic

• H01L29/7788

  Electricity · mapped topic