Formation of bottom junction in vertical FET devices

Patent metadata

Field	Value
Publication number	US-9842933-B1
Application number	US-201615180422-A
Country	US
Kind code	B1
Filing date	Jun 13, 2016
Priority date	Jun 13, 2016
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

First claim

The invention claimed is:

1. A method for use in forming a vertical FinFET device, the method comprising:
providing an intermediate semiconductor structure comprising:
a semiconductor substrate;
a fin disposed on the semiconductor substrate, the fin having a top surface, and spaced-apart vertical sides;
a mask disposed over the top surface of the fin; and
at least one spacer disposed over the vertical sides of the fin;

removing portions of the substrate to define spaced-apart recesses each extending below a respective one of the spacers;
growing semiconductor material in the recesses for a source or a drain for a bottom junction in the vertical FinFET device;
forming a gate structure adjacent to at least the vertical sides of the fin; and
forming, above the top of the fin, the other of the source or the drain for a top junction in the vertical FinFET device.

2. The method of claim 1 wherein the removing comprises removing portions of the substrate beneath the spacers and beneath a portion of the fin to define the spaced-apart recesses, and wherein the growing comprises growing the semiconductor material in the spaced-apart recesses beneath the spacers and beneath the portion of the fin.

3. The method of claim 1 wherein growing comprises epitaxially growing semiconductor material in the recesses.

4. The method of claim 1 wherein the removing comprises first removing vertical portions of the substrate adjacent to and below the spacers, and second removing portions of the substrate perpendicularly under the spacers to define the recesses.

5. The method of claim 1 wherein the recesses comprise tapering surfaces disposed under portions of the fin.

6. The method of claim 1 wherein the at least one spacer comprises a first and a second spacer, and wherein the first spacer extends under the second spacer.

7. The method of claim 1 wherein the removing comprises isotropically removing the portions of the substrate.

8. The method of claim 1 wherein the removing comprises isotropically removing portions of the substrate to define the recesses extending beneath the spacers and beneath at least a portion of the fin.

9. The method of claim 1 wherein the removing comprises anisotropically removing portions of the substrate.

10. The method of claim 1 wherein the removing comprises anisotropically removing portions of the substrate extending below the spacers, and isotropically removing portions of the substrate so that the recesses extend beneath the spacers and beneath the fin.

11. The method of claim 1 wherein the removing comprises isotropically removing portions of the substrate, and anisotropically removing portions of the substrate so that the recesses extend beneath the spacers and beneath the fin.

12. The method of claim 1 further comprising implanting in the semiconductor substrate adjacent to the recesses an implant material resulting in amorpharizing of the substrate adjacent to the recesses, removing the amorphous substrate portions to define enlarged recesses, and wherein the growing comprises growing the semiconductor material in the enlarged recesses.

13. The method of claim 1 further comprising removing the at least one spacer and forming a dielectric layer over the fin prior to forming the gate.

14. The method of claim 13 wherein the vertical FET device is a gate-all around device.

Assignees

• Globalfoundries Inc

Inventors

• Niimi Hiroaki
• Lim Kwan-Yong
• Bentley Steven John
• Chanemougame Daniel

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H01L21/30604

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L29/78642

  Electricity · mapped topic