Zero-Misalignment Via-Pad Structures

Patent metadata

Field	Value
Publication number	US-2016183370-A1
Application number	US-201414576107-A
Country	US
Kind code	A1
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

First claim

What is claimed is:

1 . A method to manufacture an electronic device, comprising:
depositing a photoresist on a seed layer on a substrate; removing a first region of the photoresist to expose a first portion of the seed layer to form a via-pad structure; depositing a first conductive layer onto the first portion; removing a second region of the photoresist adjacent to the first region to expose a second portion of the seed layer to form a line; and depositing a second conductive layer onto the first conductive layer and the second portion of the seed layer.

2 . The method of claim 1 , wherein the second conductive layer is deposited on a top portion of the first conductive layer and a sidewall portion of the first conductive layer.

3 . The method of claim 1 , wherein the first conductive layer is deposited to the thickness smaller than the thickness of the photoresist.

4 . The method of claim 1 , wherein the photoresist is a dual tone photoresist.

5 . The method of claim 1 , wherein the via-pad structure comprises a lower portion of the first conductive layer that represents a pad, and a first portion of a second conductive layer on an upper portion of the first conductive layer that represents a via portion, and wherein the line comprises a second portion of the second conductive layer on the second portion of the seed layer.

6 . The method of claim 1 , further comprising
removing a third region of the photoresist to expose a third portion of the seed layer; and removing the third portion of the seed layer.

7 . The method of claim 1 , wherein the substrate is an organic substrate.

8 . A method to provide zero misalignment via-pad structures, comprising:
depositing a seed layer on a substrate; depositing a photoresist on the seed layer; removing a first region of the photoresist to expose a first portion of the seed layer to form a via-pad structure; depositing a first conductive layer onto the first portion; removing a second region of the photoresist to expose a sidewall portion of the first conductive layer and a second portion of the seed layer to form a line; and depositing a second conductive layer on the sidewall portion of the first conductive layer.

9 . The method of claim 8 , wherein the first conductive layer is deposited to the thickness smaller than the thickness of the photoresist.

10 . The method of claim 8 , wherein the via-pad structure comprises a lower portion of the first conductive layer that represents a pad portion, and a first portion of a second conductive layer on an upper portion of the first conductive layer that represents a via portion, and wherein the line comprises a second portion of the second conductive layer on the second portion of the seed layer.

11 . The method of claim 8 , further comprising
exposing the first region of the photoresist to at least a first wavelength; and exposing the second region of the photoresist to at least a second wavelength.

12 . The method of claim 8 , further comprising
exposing the first region of the photoresist to a first light dose; and exposing the second region of the photoresist to a second light dose.

13 . The method of claim 8 , further comprising
removing a third region of the photoresist to expose a third portion of the seed layer; and removing the third portion of the seed layer.

14 . An apparatus to manufacture an electronic device, comprising
a via-pad structure over a first portion of a seed layer on a substrate; a line adjacent to the via-pad structure over a second portion of a substrate,
wherein the via-pad structure comprises a lower portion of a first conductive layer that represents a pad portion, and a first portion of a second conductive layer on an upper portion of the first conductive layer that represents a via portion.

15 . The apparatus of claim 14 , wherein the via portion comprises a sidewall extending in a direction of the line.

16 . The apparatus of claim 14 , wherein the line comprises a second portion of the second conductive layer over the second portion of the substrate.

17 . The apparatus of claim 14 , wherein the seed layer is deposited between at least one of the first conductive layer and the second conductive layer and the substrate.

18 . The apparatus of claim 14 , wherein at least one of the first conductive layer and the second conductive layer comprises copper.

19 . The apparatus of claim 14 , wherein a size of the pad portion and the size of the via portion are substantially similar.

20 . An apparatus to provide zero misalignment via-pad structures, comprising
a via-pad structure comprising a first conductive layer on a first portion of a seed layer on a substrate and a first portion of a second conductive layer on the first conductive layer; a line comprising a second portion of the second conductive layer on a second portion of the seed layer on the substrate adjacent to the via-pad structure.

21 . The apparatus of claim 20 , wherein a lower portion of the first conductive layer represents a pad portion, and the first portion of the second conductive layer on an upper portion of the first conductive layer represents a via portion.

22 . The apparatus of claim 20 , wherein the via-pad structure comprises a via sidewall extending in a direction of the line.

23 . The apparatus of claim 20 , wherein at least one of the first conductive layer and the second conductive layer comprises copper.

24 . The apparatus of claim 20 , further comprising a strip line coupled to the via-pad structure.

25 . The apparatus of claim 20 , further comprising a microstrip coupled to the via-pad structure.

Assignees

• Intel Corp

Inventors

• Rawlings Brandon M
• Braunisch Henning

Classifications

• H05K3/4679

  Aligning added circuit layers or via connections relative to previous circuit layers · CPC title

• H05K3/0082 Primary

  characterised by the exposure method of radiation-sensitive masks · CPC title

• H05K2203/0505

  Double exposure of the same photosensitive layer · CPC title

• H05K2201/09854

  Hole or via having special cross-section, e.g. elliptical · CPC title

• H05K3/4647

  by applying an insulating layer around previously made via studs · CPC title