Zero-misalignment via-pad structures

Patent metadata

Field	Value
Publication number	US-9713264-B2
Application number	US-201414576107-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

First claim

What is claimed is:

1. A method to manufacture an electronic device, comprising:
depositing a photoresist on a seed layer on a substrate, wherein the photoresist is a dual tone photoresist;
removing a first region of the photoresist to expose a first portion of the seed layer to form a via-pad structure;
depositing a first conductive layer onto the first portion;
removing a second region of the photoresist adjacent to the first region to expose a second portion of the seed layer to form a line; and
depositing a second conductive layer onto the first conductive layer and the second portion of the seed layer.

2. The method of claim 1 , wherein the second conductive layer is deposited on a top portion of the first conductive layer and a sidewall portion of the first conductive layer.

3. The method of claim 1 , wherein the first conductive layer is deposited to the thickness smaller than the thickness of the photoresist.

4. The method of claim 1 , further comprising
removing a third region of the photoresist to expose a third portion of the seed layer; and
removing the third portion of the seed layer.

5. The method of claim 1 , wherein the substrate is an organic substrate.

6. A method to manufacture an electronic device, comprising:
depositing a photoresist on a seed layer on a substrate, wherein the photoresist is a dual tone photoresist;
removing a first region of the photoresist to expose a first portion of the seed layer to form a via-pad structure;
depositing a first conductive layer onto the first portion;
removing a second region of the photoresist adjacent to the first region to expose a second portion of the seed layer to form a line; and
depositing a second conductive layer onto the first conductive layer and the second portion of the seed layer, wherein the via-pad structure comprises a lower portion of the first conductive layer that represents a pad, and a first portion of the second conductive layer on an upper portion of the first conductive layer that represents a via portion, and wherein the line comprises a second portion of the second conductive layer on the second portion of the seed layer.

7. A method to provide zero misalignment via-pad structures, comprising:
depositing a seed layer on a substrate;
depositing a photoresist on the seed layer;
removing a first region of the photoresist to expose a first portion of the seed layer to form a via-pad structure;
depositing a first conductive layer onto the first portion;
removing a second region of the photoresist to expose a sidewall portion of the first conductive layer and a second portion of the seed layer to form a line; and
depositing a second conductive layer on the sidewall portion of the first conductive layer, wherein the via-pad structure comprises a lower portion of the first conductive layer that represents a pad portion. and a first portion of the second conductive layer on an upper portion of the first conductive layer that represents a via portion, and wherein the line comprises a second portion of the second conductive layer on the second portion of the seed layer.

8. The method of claim 7 , wherein the first conductive layer is deposited to the thickness smaller than the thickness of the photoresist.

9. The method of claim 7 , further comprising
exposing the first region of the photoresist to at least a first wavelength; and
exposing the second region of the photoresist to at least a second wavelength.

10. The method of claim 7 , further comprising
exposing the first region of the photoresist to a first light dose; and
exposing the second region of the photoresist to a second light dose.

11. The method of claim 7 , further comprising
removing a third region of the photoresist to expose a third portion of the seed layer; and
removing the third portion of the seed layer.

Assignees

• Intel Corp

Inventors

• Rawlings Brandon M
• Braunisch Henning

Classifications

• H05K2203/0505

  Double exposure of the same photosensitive layer · CPC title

• H05K2201/09854

  Hole or via having special cross-section, e.g. elliptical · CPC title

• H05K2201/09463

  Partial lands, i.e. lands or conductive rings not completely surrounding the hole · CPC title

• H05K3/4679

  Aligning added circuit layers or via connections relative to previous circuit layers · CPC title

• H05K3/4647

  by applying an insulating layer around previously made via studs · CPC title