Fin-like field effect transistor (FinFET) device and method of manufacturing same

Patent metadata

Field	Value
Publication number	US-10468408-B2
Application number	US-201815898785-A
Country	US
Kind code	B2
Filing date	Feb 19, 2018
Priority date	Oct 18, 2010
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A semiconductor device includes a semiconductor substrate and two fin structures. Channels of the fin structures include a second semiconductor material portion over a first semiconductor material portion. Source and drain regions of the first fin structure include a third semiconductor material portion over the first semiconductor material portion. Source and drain regions of the second fin structure include the second semiconductor material portion over the first semiconductor material portion and a fourth semiconductor material portion over the second semiconductor material portion. The first, second, third, and fourth semiconductor material portions are different in composition from each other.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an isolation feature disposed over a semiconductor substrate;
first and second fin structures disposed over the semiconductor substrate and separated by the isolation feature, each of the first and second fin structures including:
a source region and a drain region that include a first semiconductor material layer disposed over the semiconductor substrate, a second semiconductor material layer disposed over the first semiconductor material layer, and a third semiconductor material layer disposed over the second semiconductor material layer, wherein the first and second semiconductor material layers are different in composition, the first and third semiconductor material layers are different in composition, and the second semiconductor material layer extends toward the semiconductor substrate below a top surface of the isolation feature; and
a channel defined between the source and drain regions, the channel including the first semiconductor material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first semiconductor material layer,
wherein a portion of the third semiconductor material layer of the first fin structure that extends over the isolation feature is connected to a portion of the third semiconductor material layer of the second fin structure that extends over the isolation feature, such that the third semiconductor material layer of the first fin structure merges with the third semiconductor material layer of the second fin structure.

2. The semiconductor device of claim 1 , wherein the first semiconductor material layer includes Si and each of the second and third semiconductor material layers includes Si 1-x Ge x .

3. The semiconductor device of claim 1 , wherein each of the first and second fin structures further includes a fourth semiconductor material layer disposed over the third semiconductor material layer, wherein the third and fourth semiconductor material layers are different in composition.

4. The semiconductor device of claim 3 , wherein:
the first semiconductor material layer includes Si;
the second and third semiconductor material layers includes Si 1-x Ge x ; and
the fourth semiconductor material layer includes Si 1-z Ge z , where x is not equal to z.

5. The semiconductor device of claim 4 , wherein z is less than x.

6. The semiconductor device of claim 3 , wherein the fourth semiconductor material layer of the first fin structure is connected to the fourth semiconductor material layer of the second fin structure.

7. The semiconductor device of claim 1 , wherein the second semiconductor material layer is directly attached to the first semiconductor material layer in the channel and in the source and drain regions, and the third semiconductor material layer is directly attached to the second semiconductor material layer in the source and drain regions.

8. A semiconductor device, comprising:
first and second fin structures disposed over a semiconductor substrate, each of the first and second fin structures including a source region and a drain region, and a channel defined between the source and drain regions,
a dielectric layer disposed over the semiconductor substrate and between the first fin structure and the second fin structure;
wherein the channel includes a first semiconductor material layer disposed over the semiconductor substrate and a second semiconductor material layer disposed over the first semiconductor material layer,
wherein the source and drain regions include the first semiconductor material layer disposed over the semiconductor substrate, a third semiconductor material layer disposed over the first semiconductor material layer, and a fourth semiconductor material layer disposed over the third semiconductor material layer,
wherein the first and second semiconductor material layers are different in composition, the second and third semiconductor material layers are different in composition, and the third and fourth semiconductor material layers are different in composition, and
wherein the third semiconductor material layer of the first fin structure and the third semiconductor material layer of the second fin structure are merged together to form a fin template over the dielectric layer.

9. The semiconductor device of claim 8 , wherein:
each of the first and third semiconductor material layers includes Si;
the second semiconductor material layer includes Si 1-x Ge x ; and
the fourth semiconductor material layer includes Si 1-y Ge y , where x is independent of y.

10. The semiconductor device of claim 8 , wherein the fourth semiconductor material layer of the first fin structure is connected to the fourth semiconductor material layer of the second fin structure.

11. The semiconductor device of claim 8 , wherein the second semiconductor material layer is directly attached to the first semiconductor material layer in the channel, and the third semiconductor material layer is directly attached to the first semiconductor material layer in the source and drain regions.

12. A semiconductor device, comprising:
a semiconductor substrate;
first and second fin structures disposed over the semiconductor substrate, wherein each of the first and second fin structures includes a source region and a drain region, and a channel defined between the source and drain regions,
wherein the channel of each of the first and second fin structures includes a first semiconductor material portion disposed over the semiconductor substrate and a second semiconductor material portion disposed over the first semiconductor material portion,
wherein the source and drain regions of each of the first and second fin structures include the first semiconductor material portion disposed over the semiconductor substrate,
wherein the source and drain regions of the first and second fin structures include a third semiconductor material portion disposed over and extending along the first semiconductor material portion disposed in the source and drain regions of each of the first and second fin structures;
wherein the first semiconductor material portion and the second semiconductor material portion are different in composition from each other; and

a dielectric layer disposed over the semiconductor substrate and surrounding bottom portions of the first and second fin structures, wherein the dielectric layer is disposed between the first fin structure and the second fin structure.

13. The semiconductor device of claim 12 , wherein:
the first semiconductor material portion includes Si; and
the second semiconductor material portion includes Si and Ge.

14. The semiconductor device of claim 13 , wherein the third semiconductor material portion includes Si and Ge.

15. The semiconductor device of claim 12 , the source and drain regions of each of the first and second fin structures further include the second semiconductor material portion disposed between the first semiconductor material portion and the third semiconductor material portion.

16. The semiconductor device of claim 15 , wherein an upper surface of the second semiconductor material portion in the source and drain regions of each of the first and second fin structures is lower than an upper surface of an isolation feature disposed between the first and second fin structures.

17. The semiconductor device of claim 15 , wherein a height of the second semiconductor material portion in the channel of each of the first and second fin structures is greater than a height of the second s

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Chih-Hao
• Xu Jeff J

Classifications

• H01L29/0642

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L27/0886 Primary

  Electricity · mapped topic

• H01L27/12

  Electricity · mapped topic