Shielded MRAM cell

Patent metadata

Field	Value
Publication number	US-10439129-B2
Application number	US-201815874077-A
Country	US
Kind code	B2
Filing date	Jan 18, 2018
Priority date	Jan 18, 2018
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

One illustrative integrated circuit (IC) product disclosed herein includes an MRAM cell, the MRAM cell having an outer perimeter, wherein the MRAM cell comprises a bottom electrode, a top electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the IC product also includes an insulating material positioned around the outer perimeter of the MRAM cell and a conductive sidewall spacer comprised of a metal-containing shielding material positioned around the outer perimeter of the MRAM cell, wherein the insulating material is positioned between the conductive sidewall spacer and the MRAM cell.

First claim

What is claimed:

1. An integrated circuit product, comprising:
an MRAM cell, said MRAM cell having an outer perimeter, said MRAM cell comprising:
a bottom electrode;
a top electrode; and
an MTJ (Magnetic Tunnel Junction) element positioned above said bottom electrode and below said top electrode;

an insulating material positioned around said outer perimeter of said MRAM cell;
an electrically conductive top layer of a metal-containing shielding material positioned above said MJT element; and
a metal-containing sidewall spacer comprised of a metal-containing shielding material positioned around said outer perimeter of said MRAM cell, wherein said insulating material is positioned between said metal-containing sidewall spacer and said MRAM cell, wherein said insulating material is positioned laterally between said metal-containing sidewall spacer and said MTJ element and covers vertical sidewall portions of said electrically conductive top layer of metal-containing shielding material.

2. The integrated circuit product of claim 1 , wherein said top electrode comprises a lower layer and an upper layer and wherein said electrically conductive top layer of a metal-containing shielding material is positioned above said lower layer and below said upper layer.

3. The integrated circuit product of claim 2 , further comprising an electrically conductive bottom layer of a metal-containing shielding material positioned below said MTJ element and above said bottom electrode, wherein said insulating material covers vertical sidewall portions of said electrically conductive bottom layer of metal-containing shielding material.

4. The integrated circuit product of claim 3 , wherein said metal-containing sidewall spacer, said electrically conductive top layer of metal-containing shielding material and said electrically conductive bottom layer of metal-containing shielding material all comprise a same metal-containing shielding material.

5. The integrated circuit product of claim 3 , wherein said metal-containing sidewall spacer, said electrically conductive top layer of metal-containing shielding material and said electrically conductive bottom layer of metal-containing shielding material, considered collectively, substantially encapsulate said MRAM cell.

6. The integrated circuit product of claim 5 , wherein said metal-containing sidewall spacer is an electrically conductive sidewall spacer.

7. The integrated circuit product of claim 3 , wherein said insulating material is positioned laterally between said metal-containing sidewall spacer and each of said MTJ element, said electrically conductive top layer of metal-containing shielding material and said electrically conductive bottom layer of metal-containing shielding material.

8. The integrated circuit product of claim 1 , further comprising an electrically conductive bottom layer of a metal-containing shielding material positioned below said MTJ element and above said bottom electrode, wherein said insulating material covers vertical sidewall portions of said electrically conductive bottom layer of metal-containing shielding material.

9. The integrated circuit product of claim 1 , wherein said metal-containing shielding material comprises one of a substantially pure metal, metal alloy, tungsten, tantalum, ruthenium, aluminum or platinum and wherein said metal-containing sidewall spacer has a thickness, at its base, of about 0.5-30 nm.

10. The integrated circuit product of claim 1 , wherein said metal-containing sidewall spacer comprises at least 30% metal (atomic percentage).

11. The integrated circuit product of claim 1 , wherein said metal-containing sidewall spacer is an electrically conductive sidewall spacer.

12. An integrated circuit product, comprising:
an MRAM cell, said MRAM cell having an outer perimeter, said MRAM cell comprising:
a bottom electrode;
a top electrode; and
an MTJ (Magnetic Tunnel Junction) element positioned above said bottom electrode and below said top electrode;

a conformal layer of first insulating material positioned around said outer perimeter of said MRAM cell; and
a second shielding insulating material positioned on said first insulating material and around said outer perimeter of said MRAM cell, wherein said first insulating material and said second shielding insulating material are different materials and said second shielding insulating material is in the form of an insulating shielding sidewall spacer comprised of said second shielding insulating material positioned vertically above a portion of said conformal layer of said first insulating material and is not present above at least some part of said conformal layer of said first insulating material that extends laterally between said MRAM cell and an adjacent MRAM cell.

13. The integrated circuit product of claim 12 , wherein said first insulating material comprises one of silicon dioxide, silicon nitride, nitrogen-doped silicon carbide, silicon oxynitride, silicon oxycarbide, silicon oxycarbide nitride, aluminum oxide, titanium oxide, tantalum oxide or a low-k material (k value of 8 or less) and said second shielding insulating material comprises one of silicon dioxide, silicon nitride, nitrogen-doped silicon carbide, silicon oxynitride, silicon oxycarbide, silicon oxycarbide nitride, aluminum oxide, titanium oxide, tantalum oxide or a low-k material (k value of 8 or less).

14. The integrated circuit product of claim 12 , wherein said first insulating material is in the form of a conformal layer of said first insulating material, wherein a substantially horizontally oriented portion of said conformal layer of said first insulating material extends laterally between said MRAM cell and an adjacent MUM cell.

15. The integrated circuit product of claim 14 , wherein each of said first insulating material and said second shielding insulating material have a lateral thickness at a location adjacent a mid-height of said MRAM cell that falls within a range of about 0.5-30 nm.

16. The integrated circuit product of claim 14 , wherein said insulating shielding sidewall spacer has a thickness, at its base, of about 0.5-30 nm.

17. The integrated circuit product of claim 12 , wherein said MRAM cell has a generally circular configuration when viewed from above and wherein said integrated circuit product further comprises a plurality of CMOS-based transistor devices that are formed for at least one non-memory circuit on said integrated circuit product.

Assignees

• Globalfoundries Sg Pte Ltd
• Globalfoundries Inc

Inventors

• Houssameddine Dimitri
• Wang Chenchen Jacob
• Liu Bin
• Siah Soh Yun

Classifications

• H10W42/20 Primary

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L27/222

  Electricity · mapped topic

• H01L43/02 Primary

  Electricity · mapped topic

• H01L23/552

  Electricity · mapped topic