Deuterated film encapsulation of nonvolatile charge trap memory device

Patent metadata

Field	Value
Publication number	US-8993400-B1
Application number	US-201314029500-A
Country	US
Kind code	B1
Filing date	Sep 17, 2013
Priority date	Jul 20, 2007
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.

First claim

What is claimed is:

1. A method of fabricating a nonvolatile charge trap memory device, comprising:
forming sequentially on a substrate a tunneling layer, a charge retention layer, a blocking layer, and a gate layer;
forming on the gate layer a deuterated gate cap layer;
etching the deuterated gate cap layer and the tunneling layer into a gate stack;
forming a gate stack spacer adjacent to a sidewall of the gate stack; and
forming an interlayer dielectric layer on the gate stack and the gate stack spacer, the gate cap layer having a higher deuterium concentration at an interface with the gate layer than at an interface with the interlayer dielectric layer.

2. The method of claim 1 , wherein forming on the gate layer a deuterated gate cap layer further comprises depositing silicon nitride with ND 3 .

3. The method of claim 1 , wherein depositing a deuterated gate stack spacer layer adjacent to the gate stack further comprises:
depositing a first dielectric film and a second dielectric film on the first dielectric film, wherein the second dielectric film is a silicon nitride formed with ND 3 .

4. The method of claim 3 , wherein the silicon nitride is further formed with a deuterated silicon precursor gas.

5. The method of claim 1 , wherein forming a gate layer further comprises depositing a silicon film with a deuterated silicon precursor gas.

6. The method of claim 1 , further comprising:
diffusing deuterium from the gate cap layer into at least the blocking layer with an elevated temperature anneal performed after formation of the gate stack and prior to deposition of a gate stack spacer layer.

7. A method comprising:
forming on a substrate a gate stack between a source and drain region, the gate stack including a tunneling layer, a trapping layer, a blocking layer, a gate layer, and a deuterated gate cap layer;
forming a gate stack spacer adjacent to a sidewall of the gate stack; and
forming an interlayer dielectric layer on the gate stack and the gate stack spacer, the gate cap layer having a higher deuterium concentration at an interface with the gate layer than at an interface with the interlayer dielectric layer.

8. The method of claim 7 , wherein the deuterated gate cap layer comprises deuterated silicon nitride.

9. The method of claim 7 , wherein forming the gate stack spacer comprises forming a deuterated gate stack spacer.

10. The method of claim 9 , wherein forming the deuterated gate stack spacer comprises forming a first dielectric layer adjacent to the sidewall of the gate stack and forming a second dielectric layer on the first dielectric layer and at least one of the first dielectric layer and the second dielectric layer comprises deuterated silicon nitride.

11. The method of claim 10 , wherein the first dielectric layer comprises deuterated silicon nitride and the second dielectric layer is non-deuterated.

12. The method of claim 7 , wherein the gate layer is deuterated and has a concentration of deuterium greater near an interface with the blocking layer than near the interface with the gate cap layer.

13. The method of claim 12 , wherein the gate layer is deuterated silicon.

14. The method of claim 12 , wherein the deuterated gate layer comprises a lower concentration of deuterium than does the deuterated gate cap layer.

15. The method of claim 7 , wherein the deuterated gate cap layer has a higher deposited deuterium concentration at the interface with the gate layer than at the interface with the interlayer dielectric layer.

16. A method comprising:
forming a gate stack comprising a gate layer and a deuterated gate cap layer on the gate layer;
forming a deuterated gate stack spacer adjacent to a sidewall of the gate stack, wherein the deuterated gate stack spacer includes a first dielectric layer and a second dielectric layer on the first dielectric layer and at least one of the first dielectric layer and the second dielectric layer comprises deuterated silicon nitride; and
forming an interlayer dielectric layer on the gate stack and on the gate stack spacer, wherein a deuterium concentration throughout the thickness of the deuterated silicon nitride layer has a gradient with a higher deuterium concentration proximate to the sidewall of the gate stack than proximate to the interlayer dielectric layer.

17. The method of claim 16 , wherein the deuterium concentration in the gate stack is highest in the deuterated gate cap layer.

18. The method of claim 16 , wherein the deuterated gate stack spacer has a higher concentration of deuterium than the interlayer dielectric layer.

19. The method of claim 16 , wherein the at least one of the first dielectric layer and the second dielectric layer comprising deuterated silicon nitride proximate to the gate stack has a deuterium concentration that is substantially the same as the deuterium concentration in a region proximate to the interlayer dielectric.

20. The method of claim 16 , wherein forming the gate stack comprises forming a tunneling layer on a substrate, a trapping layer on the tunneling layer, a blocking layer on the trapping layer, and the gate layer on the blocking layer, and the deuterated gate cap layer on the gate layer.

Assignees

• Cypress Semiconductor Corp

Inventors

• Ramkumar Krishnaswamy
• Jenne Fredrick B
• Koutny William C

Classifications

• H10D64/681

  having a compositional variation, e.g. multilayered · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0413 Primary

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title