Redundant magnetic tunnel junctions in magnetoresistive memory

Patent metadata

Field	Value
Publication number	US-9548095-B2
Application number	US-201514697577-A
Country	US
Kind code	B2
Filing date	Apr 27, 2015
Priority date	Aug 20, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory cell even when one of the magnetic tunnel junctions within the memory cell is defective and is no longer functional. Self-referenced and referenced reads can be used in conjunction with the multiple magnetic tunnel junction memory cells. In some embodiments, writing to the memory cell forces all magnetic tunnel junctions into a known state, whereas in other embodiments, a subset of the magnetic tunnel junctions are forced to a known state.

First claim

What is claimed is:

1. A magnetoresistive memory comprising:
a memory cell that stores a single data bit, the memory cell including:
a first magnetic tunnel junction having a first resistance; and
a second magnetic tunnel junction having a second resistance, wherein the first and second magnetic tunnel junctions are coupled in series; and

access circuitry coupled to the memory cell, wherein the access circuitry is configured to determine the single data bit stored in the memory cell based on a sum of the first and second resistances.

2. The memory of claim 1 , wherein one of the first and second resistances corresponds to a resistance for a magnetic tunnel junction in a defective state.

3. The memory of claim 1 , wherein the access circuitry includes:
a current source configured to initiate current through the memory cell;
a resistance measurement circuit configured to:
detect a first memory cell resistance across the memory cell prior to the current source initiating a first current through the memory cell to establish a first state in the memory cell; and
detect a second memory cell resistance across the memory cell after initiation of the first current; and

a comparator coupled to the resistance measurement circuit, the comparator configured to determine the single data bit stored in the memory cell based on a difference between the first memory cell resistance and the second memory cell resistance.

4. The memory of claim 3 , wherein the current source of the access circuitry is further configured to initiate a first write current through the memory cell in a first direction and a second write current through the memory cell in a second direction, wherein the first write current stores a first data value and the second write current stores a second data value.

5. The memory of claim 4 , wherein the first write current stores the first bit value by only changing state of one of the first and second magnetic tunnel junctions.

6. The memory of claim 1 , wherein the memory cell is included in an array of memory cells in the magnetoresistive memory, each memory cell in the array of memory cells storing a corresponding single data bit, wherein at least one memory cell in the array of memory cells includes a defective magnetic tunnel junction, and wherein the access circuitry is configured to determine the corresponding single data bit stored in each memory cell in the array of memory cells, including the corresponding single data bit stored in the at least one memory cell that includes a defective magnetic tunnel junction.

7. The memory of claim 1 , wherein the first and second magnetic tunnel junctions are substantially similar in structure.

8. The memory of claim 1 , wherein the first magnetic tunnel junction and the second magnetic tunnel junction have different physical dimensions.

9. The memory of claim 1 , wherein the first magnetic tunnel junction is offset vertically from the second magnetic tunnel junction within the memory.

10. The memory of claim 1 , wherein the first magnetic tunnel junction is offset horizontally from the second magnetic tunnel junction within the memory.

11. The memory of claim 1 , wherein the first and second tunnel junctions are coupled in series using a conductor within an interlayer dielectric within the memory.

12. The memory of claim 1 , wherein one of the first and second resistances corresponds to a resistance for a magnetic tunnel junction in a defective state; and
wherein the access circuitry includes:
a current source configured to initiate current through the memory cell;
a resistance measurement circuit configured to:
detect a first memory cell resistance across the memory cell prior to the current source initiating a first current through the memory cell to establish a first state in the memory cell; and
detect a second memory cell resistance across the memory cell after initiation of the first current; and
a comparator coupled to the resistance measurement circuit, the comparator configured to determine the single data bit stored in the memory cell based on a difference between the first memory cell resistance and the second memory cell resistance.

13. The memory of claim 12 , wherein the current source of the access circuitry is further configured to initiate a first write current through the memory cell in a first direction and a second write current through the memory cell in a second direction, wherein the first write current stores a first data value and the second write current stores a second data value.

14. The memory of claim 1 , wherein one of the first and second resistances corresponds to a resistance for a magnetic tunnel junction in a defective state; and wherein the first magnetic tunnel junction and the second magnetic tunnel junction have different physical dimensions.

15. The memory of claim 1 , wherein one of the first and second resistances corresponds to a resistance for a magnetic tunnel junction in a defective state; and wherein the first magnetic tunnel junction is offset vertically from the second magnetic tunnel junction within the memory.

16. The memory of claim 1 , wherein one of the first and second resistances corresponds to a resistance for a magnetic tunnel junction in a defective state; and wherein the first magnetic tunnel junction is offset horizontally from the second magnetic tunnel junction within the memory.

17. The memory of claim 1 , wherein one of the first and second resistances corresponds to a resistance for a magnetic tunnel junction in a defective state; and wherein the first and second tunnel junctions are coupled in series using a conductor within an interlayer dielectric within the memory.

18. The memory of claim 1 , wherein the first magnetic tunnel junction and the second magnetic tunnel junction are substantially similar in structure; and
wherein the access circuitry includes:
a current source configured to initiate current through the memory cell;
a resistance measurement circuit configured to:
detect a first memory cell resistance across the memory cell prior to the current source initiating a first current through the memory cell to establish a first state in the memory cell; and
detect a second memory cell resistance across the memory cell after initiation of the first current; and

a comparator coupled to the resistance measurement circuit, the comparator configured to determine the single data bit stored in the memory cell based on a difference between the first memory cell resistance and the second memory cell resistance.

19. The memory of claim 1 , wherein the first magnetic tunnel junction and the second magnetic tunnel junction have different physical dimensions; and
wherein the access circuitry includes:
a current source configured to initiate current through the memory cell;
a resistance measurement circuit configured to:
detect a first memory cell resistance across the memory cell prior to the current source initiating a first current through the memory cell to establish a first state in the memory cell; and
detect a second memory cell resistance across the memory cell after initiation of the first current; and

a comparator coupled to the resistance measurement circuit, the comparator configured to determine the single data bit stored in the memory cell based on a difference between the first memory cell resistance and the second memory cell resistance.

20. The memory of claim 1 , wherein the first magnetic tunnel junction and the second magnetic tunnel junction have differe

Assignees

• Everspin Technologies Inc

Inventors

• Houssameddine Dimitri
• Slaughter Jon

Classifications

• G11C29/74

  using duplex memories, i.e. using dual copies · CPC title

• G11C11/1695

  Protection circuits or methods · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C11/1659 Primary

  Cell access · CPC title