Leadframe and integrated circuit connection arrangement

Patent metadata

Field	Value
Publication number	US-10424666-B2
Application number	US-201715680034-A
Country	US
Kind code	B2
Filing date	Aug 17, 2017
Priority date	Feb 20, 2017
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

A semiconductor package includes a leadframe having perimeter package leads and electrical connectors, a single semiconductor die having a back-side electrical contact and front-side electrical contacts, an electrically conductive clip (“clip”), and a top semiconductor die having a frontside and a backside. The single semiconductor die includes two or more transistors. Two or more of the front-side electrical contacts of the semiconductor die are electrically coupled to and physically mounted to respective electrical contacts of the leadframe. An electrical contact surface of the clip is electrically coupled to and physically mounted to an electrical connector of the leadframe. Another electrical contact surface of the clip is physically mounted to and electrically coupled to the back-side electrical contact of the semiconductor die. The backside of the top semiconductor die is physically mounted to yet another surface of the electrically conductive clip.

First claim

What is claimed is:

1. An apparatus comprising:
a leadframe having perimeter package leads, a first electrical connector, a second electrical connector, and a third electrical connector;
a single semiconductor die having a frontside and a backside, the backside having a back-side electrical contact, the frontside having a first front-side electrical contact, and a second front-side electrical contact, the first front-side electrical contact being electrically coupled to and physically mounted to the first electrical connector, and the second front-side electrical contact being electrically coupled to and physically mounted to the second electrical connector;
an electrically conductive clip having a first electrical contact surface, a second electrical contact surface, and a third electrical contact surface, the second electrical contact surface and the third electrical contact surface being on opposite sides of a portion of the electrically conductive clip, the first electrical contact surface being electrically coupled to and physically mounted to the third electrical connector, and the second electrical contact surface being electrically coupled to and physically mounted to the back-side electrical contact of the single semiconductor die; and
a top semiconductor die having a top semiconductor frontside, a top semiconductor backside and a top semiconductor back-side electrical contact, the top semiconductor backside being physically mounted to the third electrical contact surface of the electrically conductive clip
wherein:
the single semiconductor die comprises two or more transistors and a third front-side electrical contact, the first front-side electrical contact being electrically coupled to at least one of the two or more transistors, the second front-side electrical contact being electrically coupled to at least one of the two or more transistors, the third front-side electrical contact being electrically coupled to at least one of the two or more transistors, and the back-side electrical contact being electrically coupled to at least one of the two or more transistors.

2. The apparatus of claim 1 , wherein:
the top semiconductor die is a controller die.

3. The apparatus of claim 1 , wherein:
the single semiconductor die is a power semiconductor die.

4. The apparatus of claim 1 , wherein:
the electrically conductive clip has a minimum feature size of about 100 micrometers.

5. The apparatus of claim 1 , further comprising:
a first top semiconductor front-side electrical contact of the top semiconductor die, and a second top semiconductor front-side electrical contact of the top semiconductor die, the first top semiconductor front-side electrical contact being electrically coupled to a first set of the perimeter package leads, and the second top semiconductor front-side electrical contact being electrically coupled to the third front-side electrical contact of the single semiconductor die.

6. The apparatus of claim 5 , wherein:
the two or more transistors comprise a high-side transistor and a low-side transistor;
the high-side transistor comprises a high-side source, a high-side drain, and a high-side gate;
the low-side transistor comprises a low-side source, a low-side drain, and a low-side gate; and
the third front-side electrical contact is electrically coupled to one or both of the high-side gate or the low-side gate.

7. The apparatus of claim 6 , wherein:
the high-side transistor is a p-type transistor;
the low-side transistor is an n-type transistor;
the high-side gate is electrically coupled to the third front-side electrical contact;
the low-side gate is electrically coupled to the third front-side electrical contact; and
the high-side transistor and the low-side transistor are switched simultaneously using the third front-side electrical contact.

8. The apparatus of claim 1 , wherein:
the two or more transistors comprise a high-side transistor and a low-side transistor;
the high-side transistor comprises a high-side source, a high-side drain, and a high-side gate;
the low-side transistor comprises a low-side source, a low-side drain, and a low-side gate;
the first front-side electrical contact is electrically coupled to the high-side drain;
the second front-side electrical contact electrically couples the high-side source and the low-side drain together; and
the back-side electrical contact is electrically coupled to the low-side source.

9. The apparatus of claim 8 , wherein the top semiconductor back-side electrical contact is electrically coupled to the electrically conductive clip.

10. The apparatus of claim 1 , wherein:
the leadframe comprises a fourth electrical connector;
the single semiconductor die comprises a fourth front-side electrical contact electrically coupled to and physically mounted to the fourth electrical connector;
the two or more transistors comprise a high-side transistor and a low-side transistor;
the high-side transistor comprises a high-side source, a high-side drain, and a high-side gate;
the low-side transistor comprises a low-side source, a low-side drain, and a low-side gate;
the first front-side electrical contact is electrically coupled to the high-side drain;
the second front-side electrical contact electrically couples the high-side source and the low-side drain together;
the back-side electrical contact is electrically coupled to the high-side source; and
the fourth front-side electrical contact is electrically coupled to the low-side source.

11. The apparatus of claim 10 , wherein the top semiconductor back-side electrical contact is substantially electrically isolated from the electrically conductive clip.

12. The apparatus of claim 1 , wherein:
the two or more transistors comprise a high-side transistor and a low-side transistor;
the high-side transistor comprises a high-side source, a high-side drain, and a high-side gate;
the low-side transistor comprises a low-side source, a low-side drain, and a low-side gate;
the first front-side electrical contact is electrically coupled to the high-side drain;
the back-side electrical contact electrically couples the high-side source and the low-side drain together; and
the second front-side electrical contact is electrically coupled to the low-side source.

13. The apparatus of claim 12 , wherein the top semiconductor back-side electrical contact is substantially electrically isolated from the electrically conductive clip.

14. The apparatus of claim 1 , wherein:
the two or more transistors comprise a high-side transistor and a low-side transistor;
the high-side transistor comprises a high-side source, a high-side drain, and a high-side gate;
the low-side transistor comprises a low-side source, a low-side drain, and a low-side gate;
the first front-side electrical contact is electrically coupled to the high-side drain;
the second front-side electrical contact electrically couples the high-side source and the low-side drain together; and
the low-side source is electrically coupled to the back-side electrical contact.

15. The apparatus of claim 14 , wherein the top semiconductor back-side electrical contact is electrically coupled to the electrically conductive clip.

16. The apparatus of claim 1 , wherein:
the leadframe comprises a fourth electrical connector;
the single semiconductor die comprises a fourth front-side electrical contact electrically coupled to and physically mounted to the fourth electrical connector;
the two or more transistors comprise a high-side transistor, a low-side transistor, and a second low-side transist

Assignees

• Silanna Asia Pte Ltd

Inventors

• Tu Shanghui Larry
• Stuber Michael A
• Tasbas Befruz
• Molin Stuart B
• Jiang Raymond

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/871

  Bond wires and strap connectors · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/761

  of strap connectors · CPC title