Integrating multi-output power converters having vertically stacked semiconductor chips

Patent metadata

Field	Value
Publication number	US-9373571-B2
Application number	US-201514938387-A
Country	US
Kind code	B2
Filing date	Nov 11, 2015
Priority date	Apr 11, 2013
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The first chip with its first terminal is tied to the first pad. A second chip with a second transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The second chip with its first terminal is tied to the second pad. The second terminals are connected by a discrete first metal clip and a second metal clip to respective substrate pins. A composite third chip has a third and a fourth transistor integrated so that the first terminals of the transistors are on one chip surface. The second terminals are merged into a common terminal. The patterned third terminals are on the opposite chip surface. The first terminals are vertically attached to the first and second metal clips, respectively. The common terminal is connected by a common clip to a substrate pin.

First claim

We claim:

1. An electronic multi-output device comprising:
a substrate comprising:
a first pad;
a second pad;
a plurality of pins;

a first chip with a first transistor having a first chip first terminal on one chip surface and a first chip second terminal and a first chip third terminal on an opposite chip surface, the first chip first terminal tied to the first pad;
a second chip with a second transistor having a second chip first terminal on one chip surface and the second chip second terminal and a second chip third terminal on the opposite chip surface, the second chip first terminal tied to the second pad;
the first chip second terminal and second chip second terminal connected by a discrete first clip and a discrete second metal clip to respective substrate pins; and
a composite third chip having a third transistor and a fourth transistor integrated so that a first terminal of the third transistor and a first terminal of the fourth transistor are on one chip surface, and a second terminal of the third transistor and a second terminal of the forth transistor merged into a common terminal, and a patterned third terminal of the third transistor and a patterned third terminal of the fourth transistor are on an opposite chip surface;
the first terminal of the third transistor and the first terminal of the fourth transistor vertically attached to the discrete first clip and the discrete second metal clip, respectively, and the common terminal connected by a common clip to a substrate pin.

2. The device of claim 1 the first and second pads are connected to an electrical ground potential, and the substrate pin with the common clip is connected to a V IN .

3. The device of claim 1 wherein the first, second, third and fourth transistors are drain-down MOS field-effect transistors, with the first terminals being the drain terminals, the second terminals being the source terminals, and the third terminals being the gate terminals of the respective transistors.

4. The device of claim 1 wherein the device is a power converter.

5. The device of claim 1 wherein the device is regulator.

6. The device of claim 1 wherein the substrate is a leadframe.

7. The device of claim 1 wherein the substrate is a laminate.

8. The device of claim 1 wherein the substrate is a foil.

9. The device of claim 1 wherein the chips are made of a material selected from a group including SiC, GaN, GaAs, and other III-V and II-IV compounds.

Assignees

• Texas Instruments Inc

Inventors

• Denison Marie
• Carpenter Brian Ashley
• Lopez Osvaldo Jorge
• Herbsommer Juan Alejandro
• Noquil Jonathan

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W90/762

  between stacked chips · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title