Semiconductor-on-insulator integrated circuit with back side gate

Patent metadata

Field	Value
Publication number	US-9466536-B2
Application number	US-201414451342-A
Country	US
Kind code	B2
Filing date	Aug 4, 2014
Priority date	Mar 27, 2013
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Methods for manufacturing semiconductor-on-insulator (SOI) integrated circuits are disclosed. An SOI wafer is provided having a first surface and a second surface. The substrate of the SOI wafer forms the second surface. A transistor is formed in the semiconductor layer of the SOI wafer. A handle wafer is bonded to the first surface of the SOI wafer. The substrate layer is then removed to expose a back surface of the buried insulator of the SOI wafer. Conductive material is deposited on the SOI wafer that covers the back surface of the buried insulator. The conductive material is patterned to form a second gate electrode for the transistor on the back surface of the insulator.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor-on-insulator integrated circuit comprising:
providing a semiconductor-on-insulator wafer having a first surface and a second surface, wherein the semiconductor-on-insulator wafer includes a semiconductor layer, a buried insulating layer, and a substrate layer, and wherein the substrate layer forms the second surface;
forming a transistor in the semiconductor layer, wherein forming the transistor includes forming a first gate electrode of the transistor;
bonding a handle wafer to the first surface of the semiconductor-on-insulator wafer;
after bonding the handle wafer to the first surface, removing the substrate layer to expose a back surface of the buried insulator layer;
forming a hole in the back surface of the buried insulator layer that extends through the buried insulator layer and exposes the semiconductor layer;
depositing a layer of conductive material on the semiconductor-on-insulator wafer that extends into the hole in the buried insulator layer and covers the back surface of the buried insulator layer; and
patterning the layer of conductive material to form a second gate electrode for the transistor on the back surface of the buried insulator layer;
wherein the layer of conductive material provides an electrical connection to the semiconductor layer; and
wherein the layer of conductive material provides an electrical connection to the gate electrode such that the second gate electrode and first gate electrode comprise a single circuit node in the semiconductor-on-insulator integrated circuit.

2. The method of claim 1 , wherein:
the layer of conductive material is a metal.

3. The method of claim 1 , further comprising:
forming a contact for the layer of conductive material on the semiconductor layer;
wherein the hole extends through the semiconductor layer and exposes the contact; and
wherein the contact provides an electrical connection to a bias voltage.

4. The method of claim 1 , wherein:
removing the substrate involves the use of a chemical etch; and
before the removing step, the buried insulator layer has a first thickness that is less than 400 nanometers.

5. The method of claim 4 , wherein
after the removing step, the buried insulator has a second thickness that is less than 50 nanometers smaller than the first thickness.

6. The method of claim 5 , wherein
the first gate electrode and second gate electrode are spaced so that, when an on voltage is applied to the transistor, two separate inversion layers develop in a body of the transistor.

7. A method for manufacturing a semiconductor-on-insulator integrated circuit comprising:
providing a semiconductor-on-insulator wafer having a first surface and a second surface, wherein the semiconductor-on-insulator wafer includes a semiconductor layer, a buried insulating layer, and a substrate layer, and wherein the substrate layer forms the second surface;
forming a transistor in the semiconductor layer, wherein forming the transistor includes forming a first gate electrode of the transistor;
removing the substrate layer to expose a back surface of the buried insulator layer;
forming a hole in the back surface of the buried insulator layer that extends through the buried insulator layer and exposes the semiconductor layer;
forming a layer of conductive material on the semiconductor-on-insulator wafer that extends into the hole in the buried insulator layer and covers the back surface of the buried insulator layer; and
patterning the layer of conductive material to form a second gate electrode for the transistor on the back surface of the buried insulator layer;
wherein the layer of conductive material provides an electrical connection to the gate electrode such that the second gate electrode and first gate electrode comprise a single circuit node in the semiconductor-on-insulator integrated circuit; and
wherein the layer of conductive material provides an electrical connection to the gate electrode such that the second gate electrode and first gate electrode comprise a single circuit node in the semiconductor-on-insulator integrated circuit.

8. The method of claim 7 , further comprising:
bonding a handle wafer to the first surface of the semiconductor-on-insulator wafer;
wherein the removing step is conducted after the bonding step.

9. The method of claim 7 , further comprising:
the layer of conductive material is a metal.

10. The method of claim 7 , further comprising:
forming a contact for the layer of conductive material on the semiconductor layer;
wherein the hole extends through the semiconductor layer and exposes the contact; and
wherein the contact provides an electrical connection to a bias voltage.

11. The method of claim 7 , further comprising:
removing the substrate involves the use of a chemical etch; and
before the removing step, the buried insulator layer has a first thickness that is less than 400 nanometers.

12. The method of claim 11 , wherein:
after the removing step, the buried insulator has a second thickness that is less than 50 nanometers smaller than the first thickness.

13. The method of claim 12 , wherein
the first gate electrode and second gate electrode are spaced so that, when an on voltage is applied to the first and second gate electrodes, two separate inversion layers develop in a body of the transistor.

14. A method for manufacturing a semiconductor-on-insulator integrated circuit comprising:
providing a semiconductor-on-insulator wafer having a first surface and a second surface, wherein the semiconductor-on-insulator wafer includes a semiconductor layer, a buried insulating layer, and a substrate layer, and wherein the substrate layer forms the second surface;
forming a transistor in the semiconductor layer, wherein forming the transistor includes forming a first gate electrode of the transistor;
bonding a handle wafer to the first surface of the semiconductor-on-insulator wafer;
after bonding the handle wafer to the first surface, removing the substrate layer to expose a back surface of the buried insulator layer;
after removing the substrate, forming a second insulator layer on the back surface of the buried insulator layer;
patterning the second insulator layer to expose the back surface of the buried insulator layer;
depositing a layer of conductive material on the semiconductor-on-insulator wafer that covers the second insulator layer and the exposed portion of the back surface of the buried insulator layer; and
patterning the layer of conductive material to form a second gate electrode for the transistor on the back surface of the buried insulator layer.

15. The method of claim 14 , further comprising:
forming a hole in the back surface of the buried insulator layer that extends through the buried insulator layer and exposes the semiconductor layer;
wherein the layer of conductive material provides an electrical connection to the gate electrode such that the second gate electrode and first gate electrode comprise a single circuit node in the semiconductor-on-insulator integrated circuit.

16. The method of claim 14 , wherein:
the layer of conductive material is a metal.

17. The method of claim 14 , wherein:
before the removing step, the buried insulator layer has a first thickness that is less than 50 nanometers.

18. The method of claim 14 , wherein:
the second gate electrode is coupled to an external contact.

19. The method of claim 14 , wherein:
removing the substrate involves the use of a c

Assignees

• Qualcomm Inc

Inventors

• Goktepeli Sinan
• Molin Stuart B
• Imthurn George P

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title