Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact

Patent metadata

Field	Value
Publication number	US-10083897-B2
Application number	US-201715640081-A
Country	US
Kind code	B2
Filing date	Jun 30, 2017
Priority date	Feb 20, 2017
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.

First claim

What is claimed is:

1. An apparatus comprising:
an electrically conductive paddle;
a plurality of electrically conductive perimeter package leads;
a first electrically conductive clip electrically connected to a first set of the plurality of electrically conductive perimeter package leads;
a second electrically conductive clip electrically connected to a second set of the plurality of electrically conductive perimeter package leads; and
a single semiconductor die comprising:
a front-side active layer, the front-side active layer comprising an integrated power structure having two or more transistors;
a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the electrically conductive paddle;
one or more first front-side contacts electrically coupled to at least one of the two or more transistors and to the first electrically conductive clip; and
one or more second front-side contacts electrically coupled to at least one of the two or more transistors and to the second electrically conductive clip;
wherein:
one or both of the first electrically conductive clip and the second electrically conductive clip has a minimum feature size of about 100 micrometers.

2. The apparatus of claim 1 , wherein:
the two or more transistors comprise a high-side transistor and a low-side transistor;
the high-side transistor comprises a high-side source, a high-side drain, and a high-side gate;
the low-side transistor comprises a low-side source, a low-side drain, and a low-side gate;
the one or more second front-side contacts are electrically coupled to the low-side source;
the low-side drain is electrically coupled to the high-side source;
the backside contact is electrically coupled to the high-side source; and
the one or more first front-side contacts are coupled to the high-side drain.

3. The apparatus of claim 1 , wherein:
the two or more transistors comprise a high-side transistor and a low-side transistor;
the high-side transistor comprises a high-side source, a high-side drain, and a high-side gate;
the low-side transistor comprises a low-side source, a low-side drain, and a low-side gate;
the one or more first front-side contacts are electrically coupled to the high-side drain;
the backside contact electrically couples the high-side source and the low-side drain together; and
the one or more second front-side contacts are electrically coupled to the low-side source.

4. The apparatus of claim 1 , wherein:
the two or more transistors comprise a high-side transistor, a low-side transistor, and a second low-side transistor;
the high-side transistor comprises a high-side source, a high-side drain, and a high-side gate;
the low-side transistor comprises a low-side source, a low-side drain, and a low-side gate;
the second low-side transistor comprises a second low-side source, a second low-side drain, and a second low-side gate;
the single semiconductor die comprises one or more third front-side contacts electrically coupled to the second electrically conductive clip;
the one or more first front-side contacts electrically couple the high-side source and the second low-side drain together;
the one or more second front-side contacts are electrically coupled to the high-side drain;
the one or more third front-side contacts are electrically coupled to the low-side drain; and
the backside contact electrically couples the low-side source and the second low-side source together.

5. An apparatus comprising:
an electrically conductive paddle;
a plurality of electrically conductive perimeter package leads;
a first electrically conductive clip electrically connected to a first set of the plurality of electrically conductive perimeter package leads;
a second electrically conductive clip electrically connected to a second set of the plurality of electrically conductive perimeter package leads; and
a single semiconductor die comprising:
a front-side active layer, the front-side active layer comprising an integrated power structure having two or more transistors;
a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the electrically conductive paddle;
one or more first front-side contacts electrically coupled to at least one of the two or more transistors and to the first electrically conductive clip; and
one or more second front-side contacts electrically coupled to at least one of the two or more transistors and to the second electrically conductive clip;

wherein:
the two or more transistors comprise a high-side transistor and a low-side transistor;
the high-side transistor comprises a high-side source, a high-side drain, and a high-side gate;
the low-side transistor comprises a low-side source, a low-side drain, and a low-side gate;
the one or more first front-side contacts are electrically coupled to the high-side drain;
the one or more second front-side contacts electrically couple the high-side source and the low-side drain together; and
the backside contact is electrically coupled to the low-side source.

6. An apparatus comprising:
an electrically conductive paddle;
a plurality of electrically conductive perimeter package leads;
a first electrically conductive clip electrically connected to a first set of the plurality of electrically conductive perimeter package leads;
a second electrically conductive clip electrically connected to a second set of the plurality of electrically conductive perimeter package leads; and
a single semiconductor die comprising:
a front-side active layer;
a backside portion having a backside contact electrically connected to the front-side active layer and to the electrically conductive paddle;
one or more first front-side contacts electrically connected to the front-side active layer and to the first electrically conductive clip; and
one or more second front-side contacts electrically connected to the front-side active layer and to the second electrically conductive clip;
wherein:
the front-side active layer comprises two or more transistors;
the backside contact is electrically coupled to at least one of the two or more transistors;
the one or more first front-side contacts are electrically coupled to at least one of the two or more transistors;
the one or more second front-side contacts are electrically coupled to at least one of the two or more transistors;
the two or more transistors comprise a high-side transistor and a low-side transistor;
the high-side transistor comprises a high-side source, a high-side drain, and a high-side gate;
the low-side transistor comprises a low-side source, a low-side drain, and a low-side gate;
the one or more first front-side contacts are electrically coupled to the high-side drain;
the one or more second front-side contacts electrically couple the high-side source and the low-side drain together; and
the backside contact is electrically coupled to the low-side source.

7. The apparatus of claim 6 , wherein:
the two or more transistors further comprise a second low-side transistor;
the second low-side transistor comprises a second low-side source, a second low-side drain, and a second low-side gate;
the single semiconductor die comprises one or more third front-side contacts electrically coupled to the second electrically conductive clip;
the one or more second front-side contacts electrically couple the high-side source and the second low-side drain together;
the one or more third front-side contacts are electrically coupled to the low-side drain; and
the backside contact electrically couples the low-side source and the second low-side source together.

8. A method comprising

Assignees

• Silanna Asia Pte Ltd

Inventors

• Tu Shanghui Larry
• Stuber Michael A
• Tasbas Befruz
• Molin Stuart B
• Jiang Raymond

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/466 Primary

  Tape carriers or flat leads · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title