Semiconductor device with multiple HBTS having different emitter ballast resistances

Patent metadata

Field	Value
Publication number	US-10418468-B2
Application number	US-201816182898-A
Country	US
Kind code	B2
Filing date	Nov 7, 2018
Priority date	Feb 17, 2016
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

The present disclosure relates to a semiconductor device with multiple heterojunction bipolar transistors (HBTs) that have different emitter ballast resistances. The disclosed semiconductor device includes a substrate, a first HBT and a second HBT formed over the substrate. The first HBT includes a first collector, a first base over the first collector, a first emitter over the first base, and a first cap structure over the first emitter. The second HBT includes a second collector, a second base over the second collector, a second emitter over the second base, and a second cap structure over the second emitter. Herein, the first cap structure is different from the second cap structure, such that a first emitter ballast resistance from the first cap structure is at least 1.5 times greater than a second emitter ballast resistance from the second cap structure.

First claim

What is claimed is:

1. A method comprising:
providing a first no-contact heterojunction bipolar transistor (HBT) and a second no-contact HBT formed over a substrate, wherein the first no-contact HBT comprises a first lower cap over a first emitter, a first middle cap over the first lower cap, a first ballast resistor layer over the first middle cap, and a first upper cap over the first ballast resistor layer at a top portion of the first no-contact HBT, and the second no-contact HBT comprises a second lower cap over a second emitter, a second middle cap over the second lower cap, a second ballast resistor layer over the second middle cap, and a second upper cap over the second ballast resistor layer at a top portion of the second no-contact HBT;
providing a first emitter contact to the first no-contact HBT to form a first HBT, wherein the first emitter contact is formed over the first upper cap; and
providing a second emitter contact to the second no-contact HBT to form a second HBT, wherein the second emitter contact extends through the second upper cap and the second ballast resistor layer, and extends into the second middle cap.

2. The method of claim 1 wherein a first emitter ballast resistance between the first emitter and the first emitter contact is at least 1.5 times greater than a second emitter ballast resistance between the second emitter and the second emitter contact.

3. The method of claim 1 wherein the first lower cap and the second lower cap are formed from a common lower cap layer, the first middle cap and the second middle cap are formed from a common middle cap layer, and the first upper cap and the second upper cap are formed from a common upper cap layer.

4. The method of claim 1 wherein:
the first no-contact HBT further comprises a first collector and a first base formed over the first collector, wherein the first emitter is formed over the first base; and
the second no-contact HBT further comprises a second collector and a second base formed over the second collector, wherein the second emitter is formed over the second base.

5. The method of claim 4 wherein the first collector and the second collector are formed from a common collector layer, the first base and the second base are formed from a common base layer, and the first emitter and the second emitter are formed from a common emitter layer.

6. The method of claim 4 wherein:
the first no-contact HBT and the second no-contact HBT share a common substrate;
the first no-contact HBT further comprises a first subcollector between the substrate and the first collector; and
the second no-contact HBT further comprises a second subcollector between the substrate and the second collector.

7. The method of claim 6 wherein the first subcollector and the second subcollector are formed from a common subcollector layer.

8. The method of claim 1 wherein the second ballast resistor layer is formed from a same material composition with a same doping concentration and a same thickness as the first ballast resistor layer.

9. The method of claim 1 wherein the first ballast resistor layer has a doping concentration less than 1e19/cm 3 and comprises one from a group consisting of Indium-Aluminum-Arsenide (InAlAs), Indium-Phosphide (InP), and Indium-Gallium-Arsenide (InGaAs).

10. The method of claim 9 wherein the first ballast resistor layer has a thickness between 10 Å and 1500 Å.

11. The method of claim 9 wherein:
the first lower cap and the second lower cap comprise Gallium Arsenide with a doping concentration between 1e17/cm 3 and 1e19/cm 3 ;
the first middle cap comprises Gallium-Arsenide compositionally graded into Indium-Gallium-Arsenide with a doping concentration greater than 1e19/cm 3 ; and
the first upper cap comprises Indium-Gallium-Arsenide with a doping concentration greater than 1e19/cm 3 .

Assignees

• Qorvo Us Inc

Inventors

• Zampardi Peter J
• Moser Brian G
• Rogers Thomas James

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H01L29/737 Primary

  Electricity · mapped topic

• H01L29/41708

  Electricity · mapped topic

• H01L23/5228

  Electricity · mapped topic