Emitter contact epitaxial structure and ohmic contact formation for heterojunction bipolar transistor

Patent metadata

Field	Value
Publication number	US-9608084-B2
Application number	US-201514926889-A
Country	US
Kind code	B2
Filing date	Oct 29, 2015
Priority date	Jan 16, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device includes a diffusion control layer as part of an emitter epitaxial structure. The IC device may utilize a common metallization scheme to simultaneously form an emitter contact and a base contact. Other embodiments may also be described and/or claimed.

First claim

What is claimed is:

1. A method comprising:
providing a substrate including a gallium arsenide (GaAs) base layer, an indium gallium phosphide (InGaP) emitter layer on the GaAs base layer, an indium gallium arsenide (InGaAs) layer, and a diffusion control layer on the InGaAs layer, wherein providing the diffusion control layer comprises forming alternating layers of a first material and a second material to create a super lattice structure;
selectively removing material to expose at least a portion of the InGaP emitter layer; and
performing a metallization process to simultaneously form a base contact and an emitter contact.

2. The method of claim 1 , wherein performing the metallization process comprises:
forming a first platinum (Pt) layer on the exposed portion of the InGaP emitter layer and on at least a portion of the diffusion control layer;
forming a titanium (Ti) layer on the first Pt layer;
forming a second Pt layer on the Ti layer; and
forming a gold (Au) layer on the second Pt layer.

3. The method of claim 1 , further comprising applying a mask to define at least a base contact region and an emitter contact region prior to performing the metallization process.

4. A method comprising:
forming a gallium arsenide (GaAs) base layer;
forming an indium gallium phosphide (InGaP) emitter layer on the GaAs base layer;
forming an indium gallium arsenide (InGaAs) layer; and
forming a diffusion control layer on the InGaAs layer, the diffusion control layer comprising a super lattice structure including alternating layers of a first material and a second material.

5. The method of claim 4 , wherein forming the diffusion control layer includes forming a layer of at least one of InGaP, GaAs, indium phosphide (InP), indium aluminum arsenide (InAlAs), aluminum gallium arsenide (AlGaAs), or InGaAs.

6. The method of claim 4 , wherein forming the diffusion control layer includes forming an InGaP layer having a thickness approximately equal to the thickness of the InGaP emitter layer.

7. The method of claim 4 , wherein the first material is InGaAs and the second material is one of GaAs, InP, InAlAs, InGaP or AlGaAs.

8. The method of claim 1 wherein the first material is InGaAs and the second material is one of GaAs, InP, InAlAs, InGaP or AlGaAs.

Assignees

• Triquint Semiconductor Inc
• Qorvo Us Inc

Inventors

• Henderson Timothy S
• Hurtt Sheila K

Classifications

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10D62/852

  being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP · CPC title

• H10D62/85

  being Group III-V materials, e.g. GaAs · CPC title

• H01L29/737

  Electricity · mapped topic

• H01L29/42304

  Electricity · mapped topic