Active pulse shaping of solid state photomultiplier signals
US-9869781-B2 · Jan 16, 2018 · US
US10371835B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10371835-B2 |
| Application number | US-201614992635-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 11, 2016 |
| Priority date | Jan 11, 2016 |
| Publication date | Aug 6, 2019 |
| Grant date | Aug 6, 2019 |
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A silicon photomultiplier array including a plurality of microcells arranged in rows and columns. A plurality of circuit traces connecting microcell output ports to the array pixel output port, with one or more impedance matching networks connected to at least one of the circuit traces. The impedance matching networks can be connected between each row circuit trace and the pixel output port. Impedance matching networks can be located between junctions of adjacent microcell output ports and row circuit traces.
Opening claim text (preview).
The invention claimed is: 1. A silicon photomultiplier array comprising: a plurality of microcells within the photomultiplier array, the plurality of microcells arranged in rows and columns; each of the plurality of microcells including an output port, and configured to provide a pulse waveform having pulse characteristics; a plurality of circuit traces connecting the output port of the plurality of microcells to a pixel output port of the silicon photomultiplier array; and an impedance matching circuit for each row of microcells, the impedance matching circuit connected to at least one of the circuit traces and located between a junction of each microcell output port of a last column and the pixel output port of the silicon photomultiplier array, wherein the impedance matching circuit is one of a single stub, a double stub, a lumped-element, and a stepped transmission line. 2. The silicon photomultiplier array of claim 1 , including the circuit traces constructed as transmission lines. 3. The silicon photomultiplier array of claim 2 , the transmission lines being one of a slot line, a microstrip, and a stripline. 4. The silicon photomultiplier array of claim 1 , including one impedance matching circuit connected between each circuit trace of each row and the pixel output port.
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