Solid state photomultiplier with improved pulse shape readout

Patent metadata

Field	Value
Publication number	US-9851455-B2
Application number	US-201514688008-A
Country	US
Kind code	B2
Filing date	Apr 16, 2015
Priority date	Sep 22, 2014
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Embodiments of a solid state photomultiplier are provided herein. In some embodiments, a solid state photomultiplier may include a plurality of pixels, wherein each pixel of the plurality of pixels comprises a plurality of subpixels; and a first set of buffer amplifiers, wherein each buffer amplifier of the first set of buffer amplifiers is respectively coupled to a subpixel of the plurality of subpixels.

First claim

The invention claimed is:

1. A solid state photomultiplier, comprising:
a plurality of pixels, wherein each pixel of the plurality of pixels comprises a plurality of subpixels;
a first set of buffer amplifiers, wherein each buffer amplifier of the first set of buffer amplifiers is respectively coupled to a subpixel of the plurality of subpixels, wherein the first set of buffer amplifiers are multiplexed and configured to improve a readout pulse shape of the photomultiplier; and
a control circuitry integrated into the photomultiplier and configured to: monitor a parameter of the plurality of subpixels, determine whether an adjustment of at least one of a Vbias or gain of at least one of the first set of buffer amplifiers is needed and provide a signal to the at least one of the first set of buffer amplifiers to adjust at least one of the Vbias or gain of the at least one of the first set of buffer amplifiers.

2. The solid state photomultiplier of claim 1 , wherein the buffer amplifiers are integrally formed with the subpixels.

3. The solid state photomultiplier of claim 1 , wherein each of the buffer amplifiers are coupled to one another in parallel to form a single output.

4. The solid state photomultiplier of claim 1 , wherein the first set of buffer amplifiers comprise a plurality of groups of buffer amplifiers, wherein each group of buffer amplifiers are coupled to a respective secondary buffer amplifier of a plurality of secondary buffer amplifiers.

5. The solid state photomultiplier of claim 4 , wherein the plurality of secondary buffer amplifiers are coupled to a tertiary buffer amplifier.

6. The solid state photomultiplier of claim 5 , wherein the tertiary buffer amplifier is coupled to readout electronics.

7. The solid state photomultiplier of claim 4 , wherein the plurality of secondary buffer amplifiers are coupled to readout electronics.

8. A silicon photomultiplier array, comprising:
a plurality of subpixels arranged in groups to form a pixel;
a plurality of buffer amplifiers respectively coupled to the plurality of subpixels;
a plurality of secondary buffer amplifiers, wherein each group of subpixels is coupled to a secondary buffer amplifier of the plurality of secondary buffer amplifiers, wherein the plurality of buffer amplifiers and the plurality of secondary buffer amplifiers are multiplexed and configured to improve a readout pulse shape of the photomultiplier; and
a control circuitry integrated into the array and configured to: monitor a parameter of the plurality of subpixels, determine whether an adjustment of at least one of a V bias or gain of at least one of the plurality of buffer amplifiers is needed and provide a signal to the at least one of the plurality of buffer amplifiers to adjust at least one of the V bias or gain of the at least one of the plurality of buffer amplifiers.

9. The silicon photomultiplier array of claim 8 , wherein the buffer amplifiers are integrally formed with the subpixels.

10. The silicon photomultiplier array of claim 8 , wherein each buffer amplifier of the plurality of buffer amplifiers are coupled to one another in parallel to form a single output.

11. The silicon photomultiplier array of claim 8 , wherein the plurality of secondary buffer amplifiers are coupled to a tertiary buffer amplifier.

12. The silicon photomultiplier array of claim 8 , wherein the plurality of secondary buffer amplifiers are coupled to readout electronics.

13. The silicon photomultiplier array of claim 8 , wherein the tertiary buffer amplifier is coupled to readout electronics.

14. A method for monitoring a solid state photomultiplier, comprising:
monitoring a parameter of a plurality of subpixels of a solid state photomultiplier, wherein the plurality of subpixels are arranged in groups to form a pixel, and wherein each subpixel has a buffer amplifier coupled thereto, and further wherein a plurality of the buffer amplifiers is multiplexed and configured to improve a readout pulse shape of the photomultiplier;
determining whether an adjustment of at least one of a V bias or gain of the buffer amplifier of the subpixel is needed; and
providing a signal to the buffer amplifier to adjust at least one of the V bias or gain of the buffer amplifier.

15. The method of claim 14 , wherein the parameter comprises at least one of a temperature, V bias or gain of the subpixel.

16. The method of claim 14 , wherein adjusting at least one of the V bias or gain of the buffer amplifier comprises adjusting the gain of the buffer amplifier such that the buffer amplifiers of the plurality of subpixels have a substantially uniform gain.

17. The method of claim 14 , wherein adjusting at least one of the V bias or gain of the buffer amplifier comprises adjusting the V bias at the input of the buffer amplifier while maintaining the gain of the SPPM subpixel with buffer amplifier at a constant.

18. The method of claim 14 , wherein adjusting at least one of the Vbias or gain of the buffer amplifier comprises adjusting the gain of the buffer amplifier while maintaining the Vbias at a constant.

Assignees

• Gen Electric

Inventors

• Dolinsky Sergei Ivanovich
• Guo Jianjun
• Mcdaniel David Leo
• Manjeshwar Ravindra Mohan
• Fu Geng

Classifications

• G01T1/247 Primary

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