Silicon photomultipliers with digitized micro-cells having a first one-shot pulse and a second one-shot pulse provided by an electronic circuit

Patent metadata

Field	Value
Publication number	US-9541448-B2
Application number	US-201514615806-A
Country	US
Kind code	B2
Filing date	Feb 6, 2015
Priority date	Feb 6, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A silicon photomultiplier array of microcells including a photon avalanche diode and an electronic circuit configured to provide a first one-shot pulse and a second one-shot pulse based on a detected current flowing through the photon avalanche diode. The microcells arranged in rows and columns with each microcell of a respective row connected to a respective row data bus connected to a row counter configured to count one or more first one-shot pulses for a predetermined time period, a pixel adder configured to sum the count, and a digital-to-analog converter connected to the pixel adder to convert sum to an analog signal representative of an energy readout. A timing logic circuit configured to provide a validation signal to a counter control logic circuit, and the counter control logic circuit configured to provide one of a start signal, a stop signal, and a reset signal to the row counter.

First claim

The invention claimed is:

1. A silicon photomultiplier array comprising:
a plurality of microcells fabricated on a semiconductor wafer, each microcell including a photon avalanche diode and an electronic circuit; and
the electronic circuit configured to provide a first one-shot pulse and a second one-shot pulse based on a detected current flowing through the photon avalanche diode of each respective microcell.

2. The silicon photomultiplier array of claim 1 , a duration of the first one-shot pulse controllable by an adjustable programmable value.

3. The silicon photomultiplier array of claim 2 , the summation of the first one-shot pulses representing energy readout information from the silicon photomultiplier.

4. The silicon photomultiplier array of claim 1 , the summation of the second one-shot pulses representing a timing measurement of an incident radiation exposure of the silicon photomultiplier.

5. The silicon photomultiplier array of claim 1 , including:
the plurality of microcells arranged in rows and columns;
each microcell of a respective row connected to a respective row data bus;
a row counter connected to each of the respective row data buses;
the row counter configured to count one or more first one-shot pulses for a predetermined time period;
a pixel adder connected to an output of the row counter, the pixel adder configured to sum the count of the one or more first one-shot pulses; and
a digital-to-analog converter connected to an output of the pixel adder, the digital-to-analog converter configured to convert the pixel adder sum to an analog signal representative of an energy readout.

6. The silicon photomultiplier array of claim 5 , wherein the row counter and the pixel adder are implemented as separate circuits.

7. The silicon photomultiplier array of claim 5 , wherein the row counter and the pixel adder are implemented as one circuit.

8. The silicon photomultiplier array of claim 1 , including:
the plurality of microcells arranged in rows and columns, each microcell of a respective row connected to a respective row data bus;
a row counter connected to each of the respective row data buses;
a timing logic circuit configured to provide a validation signal to a counter control logic circuit; and
the counter control logic circuit configured to provide one of a start signal, a stop signal, and a reset signal to the row counter.

9. The silicon photomultiplier array of claim 8 , the counter control logic circuit configured to monitor an output of the row counter, to compare the row counter output to a predetermined threshold in digital code, and to reset the row counter if the validation signal is not present.

10. The silicon photomultiplier array of claim 9 , the counter control logic circuit configured to reset the row counter after a predetermined integration time period if the validation signal is present.

11. The silicon photomultiplier array of claim 8 , including:
an OR gate in the counter control logic circuit, the OR gate configured to operate on the validation signal and a periodic reset signal; and
the counter control logic circuit configured to provide a reset signal to the row counter based on the OR gate operation.

12. The silicon photomultiplier array of claim 11 , including the periodic reset signal having a predetermined time period.

13. The silicon photomultiplier array of claim 8 , including band pass filters in an integrated digital accumulator, the band pass filters configured to eliminate a slow drift in energy readout.

14. The silicon photomultiplier array of claim 1 , including a comparator configured to detect the current flowing through the photon avalanche diode.

15. The silicon photomultiplier array of claim 14 , the comparator configured to operate in one of a current sense mode and a voltage sense mode.

16. The silicon photomultiplier array of claim 1 , including a summer configured to sum each of the first one-shot pulses from respective microcells, the summer configured to provide an analog signal representative of a pixel energy output.

17. The silicon photomultiplier array of claim 1 , including a trigger network configured to sum each of the second one-shot pulses from respective microcells, and to provide a digital signal representative of a pixel timing output.

18. The silicon photomultiplier array of claim 17 , the trigger network including a summing node connected to the respective microcells.

19. The silicon photomultiplier array of claim 14 , including:
the comparator configured to operate in a current sense mode; and
each microcell including a current sensing and bias circuit configured to provide a bias to the photon avalanche diode, and to sense a current flowing through the photon avalanche diode.

20. The silicon photomultiplier array of claim 19 , including current sensing and bias circuit configured to provide a current signal to an input of the comparator.

Assignees

• Gen Electric

Inventors

• Guo Jianjun
• Dolinsky Sergei Ivanovich

Classifications

• G01J2001/4466

  Avalanche · CPC title

• G01J1/4228 Primary

  arrangements with two or more detectors, e.g. for sensitivity compensation · CPC title

• G01J1/44 Primary

  Electric circuits {(for command of an exposure part G03B7/02)} · CPC title

• H04N25/773

  comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD] · CPC title

• G01T1/2985

  In depth localisation, e.g. using positron emitters; Tomographic imaging (longitudinal and transverse section imaging; apparatus for radiation diagnosis sequentially in different planes, steroscopic radiation diagnosis); (using external radiation sources A61B6/02) · CPC title