Systems and methods for minimizing silicon photomultiplier signal propagation delay dispersion and improve timing

Patent metadata

Field	Value
Publication number	US-9720109-B2
Application number	US-201514609193-A
Country	US
Kind code	B2
Filing date	Jan 29, 2015
Priority date	Dec 24, 2014
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A silicon photomultiplier array including a plurality of microcells arranged in subgroupings, each microcell of a respective subgrouping providing a pulse output in response to an incident radiation. Each microcell output interconnected by respective traces of equal length to either a summing node or an integrated buffer amplifier. Each respective summing node configured to sum the pulse outputs of a first subgroup of the microcell subgroupings, and each respective integrated buffer amplifier configured to sum the pulse outputs of each microcell of a second subgrouping, the respective integrated buffer amplifier located on the silicon photomultiplier array within the second subgroup of microcells. The plurality of microcells arranged in one of columns and rows, and a first group of the arranged plurality of microcells being a mirror image of a second group of the arranged plurality of microcells about a midpoint between one of the columns and rows.

First claim

The invention claimed is:

1. A silicon photomultiplier array comprising:
a plurality of microcells having an output providing a pulse output in response to an incident radiation;
a plurality of traces of equal length interconnecting each microcell output to one of a respective summing node and a respective integrated buffer amplifier, the integrated buffer amplifier configured to provide an output if a level of the incident radiation exceeds a threshold level;
a trigger network including a controller configured to receive a threshold level setting from a user input, the controller configured to provide a threshold level reference to the respective integrated buffer amplifier;
a trigger validation circuit configured to receive from the controller a primary threshold level and a validation threshold level, the primary threshold and the validation threshold levels each converted to an analog level by respective digital-to-analog converters;
a primary discriminator configured to compare a pixel output signal to the analog primary threshold level, and to provide an output to a delay circuit if a leading edge of the pixel output signal is above the analog primary threshold level;
a validation discriminator configured to compare the pixel output signal to the analog validation threshold level and provide an output to a first one-shot circuit if the pixel output signal is above the analog validation threshold level;
an AND gate configured to compare a delay circuit output and a first one-shot circuit output, and provide a signal to a second one-shot circuit if the comparison indicates both signals present; and
the second one-shot circuit configured to provide a pulse output to a time-to-digital converter.

2. The silicon photomultiplier array of claim 1 , including the integrated buffer amplifier is one of a unity gain voltage mode amplifier, a unity gain current mode amplifier, and a defined gain amplifier.

3. The silicon photomultiplier array of claim 1 , including:
the plurality of microcells arranged in one of columns and rows; and
a first group of the arranged plurality of microcells being a mirror image of a second group of the arranged plurality of microcells about a midpoint between one of the columns and rows.

4. The silicon photomultiplier array of claim 3 , including respective circuit traces connecting respective microcell outputs of adjacent one of columns and rows.

5. The silicon photomultiplier array of claim 1 , including:
the plurality of microcells arranged in a plurality of mirror image groupings symmetric about perpendicular midlines of the mirror image groupings; and
the microcells of each mirror image grouping being mirror images of a corresponding microcell across the perpendicular midlines of the grouping.

6. The silicon photomultiplier array of claim 5 , including one of a respective first summing node and a first respective integrated buffer amplifier connected by symmetric traces to a subset of respective mirror image groupings, the respective first summing node and the subset of respective mirror image groupings forming a first unit group.

7. The silicon photomultiplier array of claim 6 , including each respective first summing node located at a common centroid of each respective first unit group.

8. The silicon photomultiplier array of claim 6 , including respective second unit groups including one of a respective second summing node and a second respective integrated buffer amplifier, the second unit groups connected by symmetric traces to a subset of first unit groups.

9. The silicon photomultiplier array of claim 8 , including each respective second summing node located at a common centroid of each respective second unit group.

10. The silicon photomultiplier array of claim 6 , including respective third unit groups including one of a respective third summing node and a third respective integrated buffer amplifier, the third unit groups connected by symmetric traces to a subset of second unit groups.

11. The silicon photomultiplier array of claim 10 , including each respective third summing node located at a common centroid of each respective third unit group.

12. The silicon photomultiplier array of claim 1 , including the threshold level setting based on observed timing measurement performance of the silicon photomultiplier array.

13. The silicon photomultiplier array of claim 1 , including the trigger network configured to detect photon arrival to a resolution of one or more photons.

14. The silicon photomultiplier array of claim 6 including:
each microcell of the first unit group being from the first subgroup of the microcell subgroupings; and
respective second unit groups connected by symmetric traces to a subset of first unit groups, each microcell of the second unit groups being from the second subgroup of the microcell subgroupings.

15. The silicon photomultiplier array of claim 14 , including each summing node located at a common centroid of each respective unit group.

16. The silicon photomultiplier array of claim 14 , including each integrated buffer amplifier located at a common centroid of each respective unit group.

17. The silicon photomultiplier array of claim 1 , including:
a microcell coder connected to a plurality of outputs from the microcell subgroupings, the microcell coder providing a pulse coded modulated output containing information on the incident radiation response of two or more of the plurality of microcells; and
the microcell coder configured as one of a voltage mode and a current mode coder.

Assignees

• Gen Electric

Inventors

• Guo Jianjun
• Dolinsky Sergei Ivanovich

Classifications

• G01T1/248 Primary

  Silicon photomultipliers [SiPM], e.g. an avalanche photodiode [APD] array on a common Si substrate · CPC title

• G01T1/208

  Circuits specially adapted for scintillation detectors, e.g. for the photo-multiplier section · CPC title

• G01T1/2018

  Scintillation-photodiode combinations · CPC title

• G01T1/20184

  Detector read-out circuitry, e.g. for clearing of traps, compensating for traps or compensating for direct hits · CPC title