CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice

Patent metadata

Field	Value
Publication number	US-10367028-B2
Application number	US-201715842990-A
Country	US
Kind code	B2
Filing date	Dec 15, 2017
Priority date	Dec 15, 2017
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

A CMOS image sensor may include a first semiconductor chip including image sensor pixels and readout circuitry electrically connected thereto, and a second semiconductor chip coupled to the first chip in a stack and including image processing circuitry electrically connected to the readout circuitry. The processing circuitry may include a plurality of transistors each including spaced apart source and drain regions and a superlattice channel extending between the source and drain regions. The superlattice channel may include a plurality of stacked groups of layers, each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. Each transistor may further include a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

First claim

That which is claimed is:

1. A CMOS image sensor comprising:
a first semiconductor chip comprising an array of image sensor pixels and readout circuitry electrically connected thereto; and
a second semiconductor chip coupled to the first semiconductor chip in stacked relation and comprising image processing circuitry electrically connected to the readout circuitry;
the image processing circuitry comprising a plurality of transistors each comprising
spaced apart source and drain regions,
a superlattice channel extending between the source and drain regions, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and
a gate comprising a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

2. The CMOS image sensor of claim 1 wherein the plurality of transistors define counter circuits.

3. The CMOS image sensor of claim 1 wherein the first semiconductor chip further comprises an electrical interconnect layer beneath the array of image sensor pixels and defining a back side illumination (BSI) configuration therewith, the electrical interconnect layer electrically connecting the array of image sensor pixels with the readout circuitry.

4. The CMOS image sensor of claim 1 further comprising at least one lens overlying the array of image sensor pixels.

5. The CMOS image sensor of claim 1 further comprising at least one color filter overlying the array of image sensor pixels.

6. The CMOS image sensor of claim 1 further comprising a third semiconductor chip coupled with the first and second semiconductor chips in the stack and comprising a plurality of memory circuits.

7. The CMOS image sensor of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

8. The CMOS image sensor of claim 1 wherein the semiconductor monolayers comprise silicon.

9. A CMOS image sensor comprising:
a first semiconductor chip comprising an array of image sensor pixels and readout circuitry electrically connected thereto;
a second semiconductor chip coupled to the first semiconductor chip in stacked relation and comprising image processing circuitry electrically connected to the readout circuitry; and
a third semiconductor chip coupled with the first and second semiconductor chips in the stack and comprising a plurality of memory circuits;
the image processing circuitry comprising a plurality of transistors defining counter circuits, each transistor comprising
spaced apart source and drain regions,
a superlattice channel extending between the source and drain regions, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and
a gate comprising a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

10. The CMOS image sensor of claim 9 wherein the first semiconductor chip further comprises an electrical interconnect layer beneath the array of image sensor pixels and defining a back side illumination (BSI) configuration therewith, the electrical interconnect layer electrically connecting the array of image sensor pixels with the readout circuitry.

11. The CMOS image sensor of claim 9 further comprising at least one lens overlying the array of image sensor pixels.

12. The CMOS image sensor of claim 9 further comprising at least one color filter overlying the array of image sensor pixels.

13. The CMOS image sensor of claim 9 wherein the at least one non-semiconductor monolayer comprises oxygen.

14. The CMOS image sensor of claim 9 wherein the semiconductor monolayers comprise silicon.

15. A CMOS image sensor comprising:
a first semiconductor chip comprising an array of image sensor pixels and readout circuitry electrically connected thereto; and
a second semiconductor chip coupled to the first semiconductor chip in stacked relation and comprising image processing circuitry electrically connected to the readout circuitry;
the image processing circuitry comprising a plurality of transistors each comprising
spaced apart source and drain regions,
a superlattice channel extending between the source and drain regions, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, and
a gate comprising a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

16. The CMOS image sensor of claim 15 wherein the plurality of transistors define counter circuits.

17. The CMOS image sensor of claim 15 wherein the first semiconductor chip further comprises an electrical interconnect layer beneath the array of image sensor pixels and defining a back side illumination (BSI) configuration therewith, the electrical interconnect layer electrically connecting the array of image sensor pixels with the readout circuitry.

18. The CMOS image sensor of claim 15 further comprising at least one lens overlying the array of image sensor pixels.

19. The CMOS image sensor of claim 15 further comprising at least one color filter overlying the array of image sensor pixels.

20. The CMOS image sensor of claim 15 further comprising a third semiconductor chip coupled with the first and second semiconductor chips in the stack and comprising a plurality of memory circuits.

Assignees

• Atomera Inc

Inventors

• Chen Yi-Ann
• Husain Abid
• Takeuchi Hideki

Classifications

• H01L29/16

  Electricity · mapped topic

• H01L27/14645 Primary

  Electricity · mapped topic

• H01L29/1033

  Electricity · mapped topic

• H01L27/14634

  Electricity · mapped topic

• H01L27/1464

  Electricity · mapped topic