Solid-state imaging device and driving method of solid-state imaging device, and electronic equipment

Patent metadata

Field	Value
Publication number	US-9609213-B2
Application number	US-201314405045-A
Country	US
Kind code	B2
Filing date	May 30, 2013
Priority date	Jul 6, 2012
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

The solid-state imaging device of the present disclosure includes a signal processing unit including an AD converter that digitizes an analog pixel signal read from each pixel of the pixel array unit to a signal line, the signal processing unit transferring digitized pixel data at a first speed higher than a frame rate; a memory unit that stores the pixel data transferred from the signal processing unit; a data processing unit that reads pixel data at a second speed lower than the first speed from the memory unit; and a control unit that, when the pixel data is read from the memory unit, controls to stop operation of a current source connected with the signal line and operation of at least the AD converter of the signal processing unit.

First claim

The invention claimed is:

1. A solid-state imaging device comprising:
signal processing circuitry including an AD converter configured to digitize an analog pixel signal read from each pixel of a pixel array unit to a signal line, the signal processing circuitry configured to transfer digitized pixel data at a first speed higher than a frame rate;
a memory configured to store the pixel data transferred from the signal processing circuitry;
data processing circuitry configured to read pixel data at a second speed higher than the frame rate and lower than the first speed from the memory; and
control circuitry configured to, when the pixel data is read from the memory, stop operation of a current source connected with the signal line and operation of at least the AD converter of the signal processing circuitry.

2. The solid-state imaging device according to claim 1 , wherein
the control circuitry is configured to stop the operation of the current source and the operation of the AD converter on a vertical synchronization signal basis.

3. The solid-state imaging device according to claim 1 , wherein
the signal processing circuitry, the memory, the data processing circuitry, and the control circuitry are formed on at least one chip which is different from a chip on which the pixel array unit is formed, and
the solid-state imaging device has a structure in which the chip on which the pixel array unit is formed and another at least one chip are layered.

4. The solid-state imaging device according to claim 3 , wherein
the control circuitry is configured to control a circuit on the side of the chip on which the pixel array unit is formed and a circuit on the side of the other at least one chip, in synchronization with each other.

5. The solid-state imaging device according to claim 1 , wherein
the signal processing circuitry is configured to perform signal processing on the analog pixel signals read on a per-pixel-row basis from the pixels of the pixel array unit, in parallel on a per-pixel-column basis.

6. The solid-state imaging device according to claim 5 , wherein
the signal processing circuitry includes
a data latch unit configured to latch the pixel data digitized by the AD converter; and
a parallel-serial conversion unit configured to convert pixel data output from the data latch unit from parallel data to serial data, and to transfer the pixel data digitized by the AD converter to the memory by pipeline transfer.

7. The solid-state imaging device according to claim 6 , wherein
the signal processing circuitry performs digitization processing by the AD converter within one horizontal period, and transfers the digitized pixel data to the data latch unit within next one horizontal period.

8. The solid-state imaging device according to claim 5 , wherein
the signal processing circuitry includes:
a data latch unit configured to latch the pixel data digitized by the AD converter;
a data compression unit configured to compress pixel data output from the data latch unit; and
a parallel-serial conversion unit configured to convert pixel data output from the data compression unit from parallel data to serial data, and to transfer the pixel data digitized by the AD converter to the memory by pipeline transfer.

9. The solid-state imaging device according to claim 8 , wherein
the signal processing circuitry is configured to perform digitization processing by the AD converter within one horizontal period, and to transfer the digitized pixel data to the data latch unit within next one horizontal period.

10. The solid-state imaging device according to claim 5 , wherein
the signal processing circuitry includes two or more AD converters, and is configured to perform signal processing for digitization in parallel in the two or more AD converters.

11. The solid-state imaging device according to claim 10 , wherein
the two or more AD converters are arranged separately on both sides in an extending direction of the signal line of the pixel array unit.

12. The solid-state imaging device according to claim 1 , wherein
the current source, the signal processing circuitry, and the memory, connected with the signal line, are provided on a per-unit basis, the unit being formed of a predetermined number of pixels, and
the signal processing circuitry is configured to perform signal processing on the analog pixel signals, read by the unit of the predetermined number of pixels from the respective pixels of the pixel array unit, in parallel by the unit.

13. The solid-state imaging device according to claim 12 , wherein
the signal processing circuitry is configured to perform signal processing on the analog pixel signals, read by the unit of the predetermined number of pixels, in a predetermined sequence regarding the pixels in the unit.

14. The solid-state imaging device according to claim 1 , wherein
the data processing circuitry includes a decoder configured to designate a column address to the memory unit, and a sense amplifier configured to read pixel data of the designated address, and
the data processing circuitry is configured to read the pixel data from the memory through the sense amplifier and the decoder.

15. The solid-state imaging device according to claim 1 , wherein
the data processing circuitry is configured to read the pixel data from the memory during an exposure period.

16. The solid-state imaging device according to claim 1 , wherein
when the control circuitry is configured to stop the operation of the current source connected with the signal line, the control circuitry interrupts a current path between the signal line and the current source.

17. The solid-state imaging device according to claim 16 , wherein
when the control circuitry is configured to interrupt the current path between the signal line and the current source, the control circuitry is configured to apply a fixed potential to the signal line.

18. A solid-state imaging device comprising a plurality of layered chips including a chip on which a pixel array unit is formed, wherein
signal processing circuitry including an AD converter configured to digitize an analog pixel signal read from each pixel of the pixel array unit to a signal line, the signal processing circuitry configured to transfer digitized pixel data at a first speed higher than a frame rate;
a memory configured to store the pixel data transferred from the signal processing circuitry;
data processing circuitry configured to read pixel data at a second speed higher than the frame rate and lower than the first speed from the memory; and
control circuitry configured to, when the pixel data is read from the memory, stop operation of a current source connected with the signal line and operation of at least the AD converter of the signal processing circuitry,
are formed on at least one chip different from the chip on which the pixel array unit is formed.

19. A driving method of a solid-state imaging device, the method comprising,
in driving the solid-state imaging device including:
signal processing circuitry including an AD converter configured to digitize an analog pixel signal read from each pixel of a pixel array unit to a signal line, the signal processing circuitry configured to transfer digitized pixel data at a first speed higher than a frame rate;
a memory configured to store the pixel data transferred from the signal processing circuitry; and
data processing circuitry configured to read pixel data at a second speed higher than the frame rate and lower than the first s

Assignees

• Sony Corp

Inventors

• Wakabayashi Hayato

Classifications

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/79

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

• H04N25/709 Primary

  Circuitry for control of the power supply · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/75

  Circuitry for providing, modifying or processing image signals from the pixel array · CPC title