Air-gap spacers for field-effect transistors

Patent metadata

Field	Value
Publication number	US-10319627-B2
Application number	US-201615376831-A
Country	US
Kind code	B2
Filing date	Dec 13, 2016
Priority date	Dec 13, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

First claim

What is claimed is:

1. A method comprising:
forming a gate structure on a top surface of a semiconductor body;
forming a first dielectric spacer adjacent to a vertical sidewall of the gate structure;
forming a semiconductor layer on the top surface of the semiconductor body and arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located horizontally between the semiconductor layer and the vertical sidewall of the gate structure;
removing a second section of the first dielectric spacer that is located above a top surface of the semiconductor layer such that the first section of the first dielectric spacer is co-planar with the top surface of the semiconductor layer; and
forming an air-gap spacer in a space from which the second section of the first dielectric spacer is removed.

2. The method of claim 1 further comprising:
replacing the gate structure with a gate electrode; and
forming a contact extending to the top surface of the semiconductor layer,
wherein the air-gap spacer is located horizontally between the contact and a vertical sidewall of the gate electrode.

3. The method of claim 2 wherein forming the air-gap spacer in the space from which the second section of the first dielectric spacer is removed further comprises:
before the gate structure is replaced with the gate electrode, forming a second dielectric spacer adjacent to the vertical sidewall of the gate structure that is located above the first section of the first dielectric spacer and above the top surface of the semiconductor layer.

4. The method of claim 3 wherein forming the air-gap spacer in the space from which the second section of the first dielectric spacer is removed further comprises:
after the contact is formed, removing the second dielectric spacer selective to the first section of the first dielectric spacer to form the air-gap spacer.

5. The method of claim 1 wherein forming the air-gap spacer in the space from which the second section of the first dielectric spacer is removed further comprises:
forming a second dielectric spacer adjacent to the vertical sidewall of the gate structure that is located above the first section of the first dielectric spacer and above the top surface of the semiconductor layer.

6. The method of claim 5 wherein forming the air-gap spacer in the space from which the second section of the first dielectric spacer is removed further comprises:
after the second dielectric spacer is formed, forming a contact extending to the top surface of the semiconductor layer; and
after the contact is formed, removing the second dielectric spacer selective to the first section of the first dielectric spacer to form the air-gap spacer.

7. The method of claim 6 further comprising:
after the second dielectric spacer is formed, replacing the gate structure with a gate electrode,
wherein the air-gap spacer is located horizontally between the contact and a vertical sidewall of the gate electrode.

8. The method of claim 1 wherein the semiconductor body is a fin, and the semiconductor layer is formed on a source/drain region of the fin.

9. The method of claim 1 further comprising:
after the first dielectric spacer is formed, forming a second dielectric spacer adjacent to the vertical sidewall of the gate structure,
wherein the first section of the first dielectric spacer is located horizontally between the semiconductor layer and a first section of the second dielectric spacer.

10. The method of claim 9 further comprising:
before the second section of the first dielectric spacer is removed, removing a second section of the second dielectric spacer that is located above the top surface of the semiconductor layer.

11. The method of claim 9 further comprising:
before the first dielectric spacer and the second dielectric spacer are formed, forming a patterned hardmask layer stack including a first hardmask layer, a second hardmask layer on the first hardmask layer, and a third hardmask layer on the second hardmask layer,
wherein the gate structure is formed using the hardmask layer stack.

12. The method of claim 11 further comprising:
before the second section of the first dielectric spacer is removed, removing a second section of the second dielectric spacer that is located above the top surface of the semiconductor layer,
wherein the third hardmask layer is removed when the second section of the second dielectric spacer is removed.

13. The method of claim 12 wherein the second section of the first dielectric spacer masks the hardmask layer stack when the second section of the second dielectric spacer is removed from the vertical sidewall of the gate structure.

14. The method of claim 12 wherein the second hardmask layer is removed when the second section of the first dielectric spacer is removed, and further comprising:
forming a third dielectric spacer in the space from which the second section of the first dielectric spacer is removed,
wherein the air-gap spacer is formed by removing the third dielectric spacer from the space.

15. The method of claim 1 wherein the first section of the first dielectric spacer and the second section of the first dielectric spacer are composed of the same dielectric material.

16. The method of claim 1 wherein forming the first dielectric spacer adjacent to the vertical sidewall of the gate structure comprises:
depositing a conformal layer composed of a dielectric material over the gate structures; and
etching the conformal layer with an anisotropic etching process to form the first section and the second section of the first dielectric spacer.

17. The method of claim 4 wherein forming the air-gap spacer in the space from which the second section of the first dielectric spacer is removed further comprises:
after the second dielectric spacer is removed, forming a dielectric cap over space from which the second section of the first dielectric spacer is removed to seal the air-gap spacer.

18. The method of claim 6 wherein forming the air-gap spacer in the space from which the second section of the first dielectric spacer is removed further comprises:
after the second dielectric spacer is removed, forming a dielectric cap over space from which the second section of the first dielectric spacer is removed to seal the air-gap spacer.

19. The method of claim 1 further comprising:
forming a second dielectric spacer in the space from which the second section of the first dielectric spacer is removed,
wherein the first dielectric spacer is formed from a first dielectric material, and the second dielectric spacer is formed from a second dielectric material that is removable selective to the first dielectric material.

20. The method of claim 19 wherein forming the air-gap spacer in the space from which the second section of the first dielectric spacer is removed further comprises: removing the second dielectric spacer selective to the second section of the first dielectric spacer to form the air-gap spacer in the space from which the second section of the first dielectric spacer is removed.

Assignees

• Globalfoundries Inc

Inventors

• Park Chanro
• Sung Min Gyu
• Kim Hoon
• Xie Ruilong

Classifications

• H10W20/072 Primary

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/46 Primary

  comprising air gaps · CPC title

• H01L21/7682 Primary

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic