Extra gate device for nanosheet

Patent metadata

Field	Value
Publication number	US-9947593-B2
Application number	US-201615187068-A
Country	US
Kind code	B2
Filing date	Jun 20, 2016
Priority date	Dec 30, 2015
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.

First claim

Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims:

1. A semiconductor device, comprising:
a substrate;
nanosheet structures, each including a stack of alternating layers on the substrate over single gate (SG) regions and extra gate (EG) regions, the nanosheet structures each including a central gate structure region and source and drain regions on end portions of the nanosheet structures; and
the central gate structure region in the EG regions including a single semiconductor layer of the stack extending between the source and drain regions forming a channel for EG devices to enable a thicker gate dielectric for the EG devices.

2. The device as recited in claim 1 , wherein the single semiconductor layer includes a topmost semiconductor layer in the stack.

3. The device as recited in claim 1 , wherein the SG regions form SG devices and the SG devices include P-type and N-type devices.

4. The device as recited in claim 1 , wherein the EG devices include P-type and N-type devices.

5. The device as recited in claim 1 , wherein the central gate structure region includes an interface layer as a gate dielectric, wherein the interface layer further comprises an oxide and/or oxynitride.

6. The device as recited in claim 5 , further comprising a high-k dielectric material formed over the interface layer.

7. The device as recited in claim 6 , further comprising a diffusion barrier layer formed on the high-k dielectric material.

8. The device as recited in claim 7 , further comprising a work function setting material formed on the diffusion barrier layer.

9. The device as recited in claim 8 , further comprising a main conductor formed on the work function setting material.

10. The device as recited in claim 1 , wherein the single semiconductor layer includes a bottommost semiconductor layer in the stack.

11. The device as recited in claim 10 , further comprising a bottom release region formed into the substrate below the bottom most semiconductor layer in the stack and filled with a dielectric material.

Assignees

• IBM

Inventors

• Doris Bruce B
• Hook Terence B
• Wang Junli

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• Y10S977/938

  Field effect transistors, FETS, with nanowire- or nanotube-channel region · CPC title

• H01L21/823807

  Electricity · mapped topic