Inner spacer for nanosheet transistors

Patent metadata

Field	Value
Publication number	US-9923055-B1
Application number	US-201615339283-A
Country	US
Kind code	B1
Filing date	Oct 31, 2016
Priority date	Oct 31, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Embodiments are directed to a method of fabricating inner spacers of a nanosheet FET. The method includes forming sacrificial and channel nanosheets over a substrate, removing sidewall portions of the sacrificial nanosheet, and forming a dielectric that extends over the channel nanosheet and within a space that was occupied by the removed sidewall portions of the sacrificial nanosheet. The method further includes forming a top protective spacer over the channel nanosheet and the dielectric, as well as applying a directional etch to the top protective spacer, the channel nanosheet, and the dielectric, wherein the directional etch is configured to be selective to the channel nanosheet and the dielectric, wherein the directional etch is configured to not be selective to the top protective spacer, and wherein applying the directional etch etches portions of the channel nanosheet and portions of the flowable dielectric that are not under the top dielectric.

First claim

What is claimed is:

1. A method of fabricating inner spacers of a nanosheet field effect transistor, the method comprising:
forming a sacrificial nanosheet and a channel nanosheet over a substrate;
removing a sidewall portion of the sacrificial nanosheet;
forming a dielectric that extends over the channel nanosheet and within a space that was occupied by the removed sidewall portion of the sacrificial nanosheet;
forming a top protective spacer over the channel nanosheet and the dielectric; and
applying a directional etch to the top protective spacer, the channel nanosheet, and the dielectric, wherein the directional etch is configured to be selective to the channel nanosheet and the dielectric, wherein the directional etch is configured to not be selective to the top protective spacer, wherein applying the directional etch etches a portion of the channel nanosheet and a portion of the dielectric that are not under the top protective spacer.

2. The method of claim 1 , wherein the portion of the dielectric that is under the top protective spacer and within the space that was occupied by the removed sidewall portion of the sacrificial nanosheet comprises a diffusion block.

3. The method of claim 2 , wherein, subsequent to applying the directional etch, a vertical sidewall of the diffusion block is substantially planar with a vertical sidewall of the channel nanosheet.

4. The method of claim 3 further comprising forming a source region and a drain region such that the diffusion block is between the sacrificial nanosheet and at least one of the source region and the drain region.

5. The method of claim 4 further comprising removing the sacrificial layer using a sacrificial nanosheet removal process, wherein the diffusion block prevents the sacrificial nanosheet removal process from also removing portions of at least one of the source region and the drain region.

6. The method of claim 5 further comprising forming a gate region around the channel nanosheet, wherein the gate region is configured to control a flow of current from the source region through the channel nanosheet into the drain region.

7. The method of claim 5 further comprising providing dopant in the source region or the drain region to form at least one junction.

8. The method of claim 7 , wherein the at least one junction comprises an extension junction of the channel nanosheet.

9. The method of claim 5 , wherein the sacrificial nanosheet removal process comprises a wet process.

10. The method of claim 9 , wherein a selectivity of the wet process to the diffusion block is below a predetermined threshold.

11. The method of claim 9 , wherein the wet process comprises an etch.

12. The method of claim 11 , wherein the etch comprises a reactive ion etch.

13. The method of claim 12 , wherein the reactive ion etch causes an etch rate of the diffusion block that is below a predetermined threshold.

14. The method of claim 1 , wherein forming of the sacrificial nanosheet and the channel nanosheet comprises forming a stack comprising alternating sacrificial nanosheets and channel nanosheets.

15. The method of claim 14 , wherein:
the top protective spacer comprises hafnium oxide;
the dielectric comprises silicon nitride;
the sacrificial nanosheet comprises silicon germanium; and
the channel nanosheet comprises silicon.

16. A method of fabricating inner spacers of a nanosheet field effect transistor, the method comprising:
forming a substrate;
forming a sacrificial nanosheet over the substrate;
forming a channel nanosheet over the sacrificial nanosheet;
forming a dummy gate over the channel nanosheet;
removing a sidewall portion of the sacrificial nanosheet;
forming a dielectric that extends over the channel nanosheet and within a space that was occupied by the removed sidewall portion of the sacrificial nanosheet;
forming a top protective spacer over the dummy gate, wherein the top protective spacer comprises a predetermined width dimension; and
applying a directional etch to the top protective spacer, the channel nanosheet, and the dielectric;
wherein the directional etch is configured to be selective to the channel nanosheet and the dielectric;
wherein the directional etch is configured to not be selective to the top protective spacer;
wherein applying the directional etch etches a portion of the channel nanosheet and a portion of the dielectric that are not under the top protective spacer;
wherein the portion of the dielectric that is under the top protective spacer and within the space that was occupied by the removed sidewall portion of the sacrificial nanosheet comprises a diffusion block;
wherein, subsequent to applying the directional etch, a width dimension of the channel substrate is substantially the same as the width dimension of the channel nanosheet;
wherein, subsequent to applying the directional etch, a vertical sidewall of the diffusion block is substantially planar with a vertical sidewall of the channel nanosheet.

17. The method of claim 16 further comprising:
forming a source region and a drain region such that the diffusion block is between the sacrificial nanosheet and at least one of the source region and the drain region; and
removing the sacrificial layer using a sacrificial nanosheet removal process;
wherein the diffusion block prevents the sacrificial nanosheet removal process from also removing portions of at least one of the source region and the drain region.

18. The method of claim 17 , wherein:
the sacrificial nanosheet removal process comprises a wet process;
a selectivity of the wet process to the diffusion block is below a predetermined threshold.

19. The method of claim 16 , wherein:
the top protective spacer comprises hafnium oxide;
the dielectric comprises silicon nitride;
the sacrificial nanosheet comprises silicon germanium; and
the channel nanosheet comprises silicon.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Xie Ruilong
• Yamashita Tenko
• Yeh Chun-Chen

Classifications

• H01L21/3065

  Electricity · mapped topic

• H01L29/0665 Primary

  Electricity · mapped topic

• H01L29/66553

  Electricity · mapped topic

• H01L21/30608

  Electricity · mapped topic

• H01L21/31111

  Electricity · mapped topic