Silicon and silicon germanium nanowire formation

Patent metadata

Field	Value
Publication number	US-9634091-B2
Application number	US-201514929504-A
Country	US
Kind code	B2
Filing date	Nov 2, 2015
Priority date	Aug 20, 2013
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

First claim

What is claimed is:

1. A semiconductor arrangement, comprising:
a first nanowire transistor formed on a substrate, the first nanowire transistor comprising:
a first germanium nanowire channel formed between a first source region and a first drain region, wherein a distance between a surface of the substrate underlying the first germanium nanowire channel and a bottom surface of the first germanium nanowire channel corresponds to a first distance;
a second germanium nanowire channel formed between the first source region and the first drain region, wherein the second germanium nanowire channel overlies the first germanium nanowire channel;
a first dielectric layer surrounding a circumference of the first germanium nanowire channel;
a second dielectric layer surrounding a circumference of the second germanium nanowire channel; and
a gate electrode formed around the first dielectric layer and the second dielectric layer, wherein a space between the first dielectric layer and the second dielectric layer is void of the gate electrode; and

a second nanowire transistor formed on the substrate, the second nanowire transistor comprising:
a first silicon nanowire channel formed between a second source region and a second drain region, wherein a distance between a surface of the substrate underlying the first silicon nanowire channel and a bottom surface of the first silicon nanowire channel corresponds to a second distance different than the first distance.

2. The semiconductor arrangement of claim 1 , wherein a first interface is defined between the first germanium nanowire channel and the first source region and a second interface is defined between the second germanium nanowire channel and the first source region.

3. The semiconductor arrangement of claim 1 , wherein a diameter of the first silicon nanowire channel is different than a diameter of the first germanium nanowire channel.

4. The semiconductor arrangement of claim 1 , wherein a diameter of the first silicon nanowire channel is between about 20% and about 40% larger than a diameter of the first germanium nanowire channel.

5. The semiconductor arrangement of claim 2 , wherein a third interface is defined between the first germanium nanowire channel and the first drain region and a fourth interface is defined between the second germanium nanowire channel and the first drain region.

6. A semiconductor arrangement, comprising:
a first nanowire transistor comprising:
a first germanium nanowire channel formed between a first source region and a first drain region;
a second germanium nanowire channel formed between the first source region and the first drain region, wherein the second germanium nanowire channel overlies the first germanium nanowire channel; and
an interfacial layer surrounding the first germanium nanowire channel and the second germanium nanowire channel, wherein the interfacial layer pinches off a space between the first germanium nanowire channel and the second germanium nanowire channel; and

a second nanowire transistor comprising:
a first silicon nanowire channel formed between a second source region and a second drain region.

7. The semiconductor arrangement of claim 6 , comprising:
a dielectric layer surrounding the interfacial layer; and
a gate electrode surrounding the dielectric layer.

8. The semiconductor arrangement of claim 6 , wherein:
the first nanowire transistor and the second nanowire transistor are formed on a substrate,
a distance between a surface of the substrate underlying the first germanium nanowire channel and a bottom surface of the first germanium nanowire channel corresponds to a first distance, and
a distance between a surface of the substrate underlying the first silicon nanowire channel and a bottom surface of the first silicon nanowire channel corresponds to a second distance different than the first distance.

9. The semiconductor arrangement of claim 6 , wherein the second nanowire transistor comprises:
a second silicon nanowire channel formed between the second source region and the second drain region.

10. The semiconductor arrangement of claim 6 , wherein the interfacial layer contacts the first germanium nanowire channel.

11. The semiconductor arrangement of claim 7 , wherein the dielectric layer contacts the interfacial layer.

12. The semiconductor arrangement of claim 6 , wherein the first germanium nanowire channel is cylindrically shaped.

13. A semiconductor arrangement, comprising:
a substrate;
a PMOS nanowire transistor overlying the substrate comprising:
a first nanowire channel formed between a first source region and a first drain region;
a second nanowire channel formed between the first source region and the first drain region;
a first dielectric layer surrounding a circumference of the first nanowire channel;
a second dielectric layer surrounding a circumference of the second nanowire channel; and
a gate electrode formed around the first dielectric layer and the second dielectric layer, wherein a space between the first dielectric layer and the second dielectric layer is void of the gate electrode; and

an NMOS nanowire transistor overlying the substrate comprising:
a third nanowire channel formed between a second source region and a second drain region.

14. The semiconductor arrangement of claim 13 , wherein the NMOS nanowire transistor comprises a fourth nanowire channel overlying the third nanowire channel and formed between the second source region and the second drain region.

15. The semiconductor arrangement of claim 13 , wherein the second nanowire channel overlies the first nanowire channel.

16. The semiconductor arrangement of claim 13 , wherein:
a distance between a surface of the substrate and a bottom surface of the first nanowire channel corresponds to a first distance, and
a distance between the surface of the substrate and a bottom surface of the third nanowire channel corresponds to a second distance different than the first distance.

17. The semiconductor arrangement of claim 13 , wherein a first interface is defined between the first nanowire channel and the first source region and a second interface is defined between the second nanowire channel and the first source region.

18. The semiconductor arrangement of claim 17 , wherein a third interface is defined between the first nanowire channel and the first drain region and a fourth interface is defined between the second nanowire channel and the first drain region.

19. The semiconductor arrangement of claim 13 , wherein the first nanowire channel is cylindrically shaped.

20. The semiconductor arrangement of claim 13 , wherein a diameter of the third nanowire channel is different than a diameter of the first nanowire channel.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ching Kuo-Cheng
• Diaz Carlos H
• Colinge Jean-Pierre

Classifications

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H01L29/66439

  Electricity · mapped topic