Audio amplifiers

Patent metadata

Field	Value
Publication number	US-10256777-B2
Application number	US-201715443889-A
Country	US
Kind code	B2
Filing date	Feb 27, 2017
Priority date	Feb 29, 2016
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

Certain aspects of the present disclosure provide amplifiers. Certain aspects of the present disclosure provide methods and apparatus for protecting an such amplifiers, for example an audio amplifier, or a delta-sigma modulator from saturation. One example amplifier generally includes an output stage comprising a plurality of transistors; and a feedback network having an input coupled to an output of the output stage and comprising a plurality of integrators connected in series. At least one of the plurality of integrators generally includes an operational amplifier having an input and an output, a first resistive element coupled to the input of the operational amplifier, a capacitive element coupled between the input and the output of the operational amplifier; and a first switch coupled between the input and the output of the operational amplifier. For certain aspects, the amplifier may be a class-D amplifier or a direct digital feedback amplifier (DDFA).

First claim

What is claimed is:

1. An amplifier comprising:
an integrator comprising at least three integrator stages coupled in series; and
control circuitry coupled to the integrator and configured to maintain a mode of a first or a last integrator stage of the at least three integrator stages and to modify a mode of at least one intermediate integrator stage of the at least three integrator stages while maintaining the mode of the first or the last integrator stage, wherein the control circuitry is configured to modify the mode of the at least one intermediate integrator stage by discharging a capacitive element in a feedback network of the at least one intermediate integrator stage.

2. The amplifier of claim 1 , further comprising:
an output stage comprising a plurality of transistors connected in a push-pull configuration, wherein the feedback network has an input coupled to the output stage and comprising the integrator.

3. The amplifier of claim 2 , wherein the control circuitry is further configured to modify the mode of the at least one intermediate integrator stage by resetting the at least one intermediate integrator stage based on a variation in at least one of an input signal for the amplifier, an output signal of the feedback network, or one or more output signals of the at least three integrator stages.

4. The amplifier of claim 3 , wherein the input signal comprises an audio input signal.

5. The amplifier of claim 1 , wherein the at least three integrator stages comprise five integrator stages and wherein the control circuitry is configured to modify modes of three intermediate integrator stages of the five integrator stages.

6. The amplifier of claim 1 , wherein the control circuitry is configured to modify the mode of the at least one intermediate integrator stage by connecting a resistive element in parallel with another capacitive element in the feedback network of the at least one intermediate integrator stage.

7. The amplifier of claim 1 , wherein the control circuitry is configured to maintain the mode of the last integrator stage and to modify the mode of the first integrator stage.

8. The amplifier of claim 1 , wherein the integrator comprises a digital integrator and wherein the control circuitry is further configured to modify the mode of the at least one intermediate integrator stage by modulating one or more coefficients for the at least one intermediate integrator stage.

9. A method of operating an amplifier comprising a plurality of integrators and an analog-to-digital converter (ADC), comprising:
generating an amplified signal in the amplifier based on an input signal; and
resetting at least one of the integrators based on a variation in at least one of the input signal, an output of the ADC, or one or more outputs of the integrators, wherein the resetting comprises closing a switch connected in parallel with a capacitive element of the at least one of the integrators to discharge the capacitive element.

10. The method of claim 9 , wherein the resetting comprises resetting all but one of the integrators.

11. The method of claim 10 , wherein the plurality of integrators are arranged in a series and wherein the one integrator is a last integrator in the series.

12. The method of claim 9 , wherein the resetting comprises closing a switch to connect a resistive element in parallel with another capacitive element of the at least one of the integrators.

13. The method of claim 9 , further comprising comparing the input signal, the output of the ADC, or an output of one of the integrators with a threshold, wherein the resetting is based on the input signal, the output of the ADC, or the output of the one of the integrators being greater than the threshold.

14. The method of claim 9 , wherein the resetting is based on the output of the ADC being saturated.

15. The method of claim 9 , wherein the amplifier comprises a direct digital feedback amplifier.

16. An amplifier comprising:
an output stage comprising a plurality of transistors; and
a feedback network having an input coupled to an output of the output stage and comprising a plurality of integrators connected in series, wherein at least one of the plurality of integrators comprises:
an operational amplifier having an input and an output;
a first resistive element coupled to the input of the operational amplifier;
a first capacitive element coupled between the input and the output of the operational amplifier; and
a first switch coupled between the input and the output of the operational amplifier, wherein a first terminal of the first switch is coupled to the input of the operational amplifier, and a second terminal of the first switch is coupled to the output of the operational amplifier.

17. The amplifier of claim 16 , wherein the at least one of the integrators further comprises a second switch connected in series with a second resistive element and wherein the second switch and the second resistive element are coupled between the input and the output of the operational amplifier.

18. The amplifier of claim 16 , wherein the at least one of the integrators further comprises a second capacitive element connected in series with a second switch and wherein the second capacitive element and the second switch are coupled between the input and the output of the operational amplifier.

19. The amplifier of claim 16 , further comprising one or more comparators, wherein at least one of the comparators has a first input coupled to the output of the operational amplifier and a second input coupled to a threshold voltage source.

20. The amplifier of claim 16 , wherein the feedback network further comprises:
a summation circuit having an input coupled to one or more outputs of the plurality of integrators; and
an analog-to-digital converter (ADC) having an input coupled to an output of the summation circuit.

21. The amplifier of claim 20 , further comprising circuitry configured to:
monitor at least one of an input signal for the amplifier, an output of the ADC, or one or more outputs of the plurality of integrators to detect a triggering event; and
reset one or more of the plurality of integrators if the triggering event is detected.

22. The amplifier of claim 21 , wherein the circuitry is configured to reset the one or more of the plurality of integrators by resetting all but one of the plurality of integrators.

23. The amplifier of claim 21 , further comprising a comparator configured to compare an output of one of the plurality of integrators with a threshold, wherein the triggering event comprises the output of the one of the plurality of integrators being greater than the threshold.

24. The amplifier of claim 21 , wherein the circuitry is configured to monitor the at least one of the input signal, the output of the ADC, or the one or more outputs of the plurality of integrators by comparing the input signal, the output of the ADC, or an output of one of the plurality of integrators with a threshold and wherein the triggering event comprises the input signal, the output of the ADC, or the output of the one of the plurality of integrators being greater than the threshold.

25. The amplifier of claim 21 , wherein the triggering event comprises the output of the ADC being saturated.

26. The amplifier of claim 16 , wherein the amplifier comprises a direct digital feedback amplifier and wherein the feedback network comprises a delta

Assignees

• Qualcomm Inc

Inventors

• Cope William
• Aschieri Julian
• Saraf Tomer

Classifications

• H03F2200/78

  A comparator being used in a controlling circuit of an amplifier · CPC title

• H03F2200/03

  the amplifier being designed for audio applications · CPC title

• H03M3/49

  in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values · CPC title

• H03M3/492

  in feed forward mode, i.e. by determining the range to be selected directly from the input signal · CPC title

• H03F2200/426

  the amplifier comprising circuitry for protection against overload · CPC title