Linear device value estimating method, capacitance detection method, integrated circuit, touch sensor system, and electronic device

US8942937B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8942937-B2
Application numberUS-201214128907-A
CountryUS
Kind codeB2
Filing dateMay 22, 2012
Priority dateJun 27, 2011
Publication dateJan 27, 2015
Grant dateJan 27, 2015

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Abstract

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A capacitance distribution detection circuit includes a multiplexer, a driver, and a sense amplifier. The multiplexer switches states between a first connection state and a second connection state. The first connection state drives first signal lines in parallel so that voltages are applied, outputs, along second signal lines, a linear sum of electric charges stored in capacitors corresponding to that respective one of the second signal lines, and estimates, a capacitance of capacitors formed along that second signal line. The second connection state drives, the second signal lines in parallel so that voltages are applied, outputs, along the first signal lines, a linear sum of electric charges stored in the capacitors corresponding to that respective one of the first signal lines, and estimates, a capacitance of the capacitors formed along that first signal line.

First claim

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The invention claimed is: 1. A method of estimating a linear device value, to detect a distribution of values of a plurality of linear devices that are each formed on intersections of a plurality of first signal lines with a plurality of second signal lines, the method comprising the steps of: driving, in drive sections, the first signal lines in a first timing, to output from the second signal lines to the estimation sections outputs that correspond to the linear devices, where…

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What does patent US8942937B2 cover?
A capacitance distribution detection circuit includes a multiplexer, a driver, and a sense amplifier. The multiplexer switches states between a first connection state and a second connection state. The first connection state drives first signal lines in parallel so that voltages are applied, outputs, along second signal lines, a linear sum of electric charges stored in capacitors corresponding …
Who is the assignee on this patent?
Miyamoto Masayuki, Iizuka Kunihiko, Sharp Kk
What technology area does this patent fall under?
Primary CPC classification G01R27/2605. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).