Apparatus for overload recovery of an integrator in a sigma-delta modulator

Patent metadata

Field	Value
Publication number	US-9680496-B2
Application number	US-201514751063-A
Country	US
Kind code	B2
Filing date	Jun 25, 2015
Priority date	Jun 25, 2015
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.

First claim

We claim:

1. An apparatus comprising:
a first integrator to receive an input signal and to generate a first output;
a second integrator to receive the first output or a version of the first output and is to generate a second output;
an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit which is to detect an overload condition in the second output;
a first digital-to-analog converter (DAC); and
a second DAC, wherein at least one of the first and second DACs is coupled to the ADC,
wherein the detection circuit comprises logic to detect at least two consecutive cycles of the overload condition in the second output.

2. The apparatus of claim 1 , wherein the logic is to generate an output indicating whether the overload condition is detected.

3. The apparatus of claim 2 , wherein the first DAC is to provide a first analog signal which is combined with the input signal, and wherein the first DAC is to adjust a signal attribute of the first analog signal according to at least a part of the digital representation and independent of the output of the logic of the detection circuit.

4. The apparatus of claim 2 , wherein the second DAC is to provide a second analog signal which is combined with the first output from the first integrator, and wherein the second DAC is to adjust a signal attribute of the second analog signal according to at least a part of the digital representation and the output of the logic of the detection circuit.

5. The apparatus of claim 4 , wherein the signal attribute is a current, and wherein the output of the detection circuit is to increase the current of the second DAC.

6. The apparatus of claim 4 comprises a bias generator which is to receive the output of the detection circuit and to adjust a bias for the second DAC.

7. The apparatus of claim 2 , wherein the ADC includes a comparator to provide an output for the detection circuit, and wherein the comparator is in addition to comparators of the ADC used for quantizing the second output into the digital representation.

8. The apparatus of claim 1 , wherein the overload condition occurs when the second output reaches voltage levels of at least one of the power rails.

9. The apparatus of claim 1 , wherein the first and second integrators are differential integrators.

10. A sigma-delta modulator comprising:
a loop filter having at least two integrators;
an analog-to-digital converter (ADC) to quantize an output of the loop filter into a digital representation, the ADC including a detection circuit which is to detect an overload condition in the output of the loop filter; and
two digital-to-analog converters (DACs) at least one of which is coupled to the ADC, wherein the detection circuit comprises logic to detect at least two consecutive cycles of the overload condition in the second output.

11. The sigma-delta modulator of claim 10 , wherein the logic is to generate an indicator indicating whether the overload condition is detected.

12. The sigma-delta modulator of claim 11 , wherein at least one of the DACs is to provide a first analog signal which is combined with an input signal to be received by at least one of the integrators, and wherein the at least one of the DACs is to adjust a signal attribute of the first analog signal according to at least a part of the digital representation and independent of the output of the detection circuit.

13. The sigma-delta modulator of claim 11 , wherein at least one of the DACs is to provide a second analog signal which is combined with an output of at least one of the integrators, and wherein the at least one of the DACs is to adjust a signal attribute of the second analog signal according to at least a part of the digital representation and the output of the detection circuit.

14. The sigma-delta modulator of claim 11 , wherein at least one of the DACs is to receive a bias independent of the output of the detection circuit.

15. The sigma-delta modulator of claim 11 , wherein at least one of the DACs is to receive a bias dependent on the output of the detection circuit.

16. The sigma-delta modulator of claim 10 , wherein the ADC includes a comparator to provide an output for the detection circuit, and wherein the comparator is in addition to comparators of the ADC used for quantizing the output into the digital representation.

17. A system comprising:
an antenna;
an integrated circuit (IC) coupled to the antenna, the IC including a sigma-delta modulator comprising:
a loop filter having at least two integrators; and
an analog-to-digital converter (ADC) to quantize an output of the loop filter into a digital representation, the ADC including a detection circuit which is to detect an overload condition in the output of the loop filter; and

a processor coupled to the IC; and
at least two digital-to-analog converters (DACs), at least one of which is coupled to the ADC.

18. The system of claim 17 , wherein the detection circuit comprises logic to detect at least two cycles of the overload condition in the output, and wherein the logic is to generate an indicator indicating whether the overload condition is detected.

19. The system of claim 17 , wherein at least one of the DACs is to receive a bias independent of the output of the detection circuit, and wherein at least one of the DACs is to receive a bias dependent on the output of the detection circuit.

Assignees

• Intel Ip Corp
• Intel Corp

Inventors

• Kauffman John G
• Dufrene Krzysztof

Classifications

• H03M1/06

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title

• H03M1/10

  Calibration or testing · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M1/00

  Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title