Gated CDS integrator

Patent metadata

Field	Value
Publication number	US-9985594-B2
Application number	US-201514847907-A
Country	US
Kind code	B2
Filing date	Sep 8, 2015
Priority date	Apr 2, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

A Gated CDS Integrator (GCI) may amplify low-level signals without introducing excessive offset and noise. The GCI may also amplify the low level signals with accurate and variable gain. The GCI may include a modulator preceding a linear amplifier such that offset or noise present in a signal path between the modulator and a demodulator input is translated to a higher out of band frequency.

First claim

The invention claimed is:

1. An apparatus, comprising:
a modulator preceding a linear amplifier such that offset or noise present in a signal path between the modulator and a demodulator input is translated to a higher out of band frequency; wherein the demodulator comprises a CDS-integrator configured to demodulate a signal present at an output of the linear amplifier, after a counter and the CDS-integrator are reset and a first switch is closed.

2. The apparatus of claim 1 , wherein the linear amplifier is between the modulator and a first capacitor, wherein
the first capacitor precedes the first switch.

3. The apparatus of claim 1 , further comprising:
a second switch in series with a second capacitor and a third switch in parallel with a third capacitor, both switch-capacitor networks in parallel in a feedback loop of a transconductance amplifier, wherein the second switch and the third switch are turned on to reset the CDS-integrator when the counter is reset.

4. The apparatus of claim 3 , wherein the first switch and the third switch are opened and the second switch is closed, when the counter reaches a predefined value.

5. The apparatus of claim 4 , wherein the CDS-integrator is configured to accumulate charge on a second capacitor, to partially deplete the charge on the second capacitor with the third capacitor and hold an accumulated charge on the second capacitor and the third capacitor when the counter reaches the predefined value.

6. The apparatus of claim 4 , wherein the predefined value is a number of cycles for which the CDS-integrator integrates and the second switch and third switch are controlled with non-overlapping clock signals to accumulate charge on the second capacitor and to partially deplete the charge on the second capacitor with the third capacitor.

7. An apparatus, comprising:
a Gated CDS Integrator configured to filter a chopped signal with correlated double sampling and discrete time lossy integration to reduce offset, 1/f, Johnson, and shot noise, wherein
the Gated CDS Integrator is further configured to digitally control discrete time amplification, and demodulate and filter the chopped signal; wherein the Gated CDS Integrator further comprises
a comparator configured to compare an output of a counter and a register, and when an output of the counter and an output of the register are same, output a logic signal to open a first switch and a third switch and close a second switch, allowing a voltage to be held for digitizing.

8. The apparatus of claim 7 , wherein the Gated CDS Integrator comprises
a modulator configured to further chop the chopped signal into a square wave with a period, translating an input signal up to harmonics of a chop clock frequency, wherein
the period alternates between an input voltage and a reference voltage.

9. The apparatus of claim 8 , wherein the modulator precedes a linear amplifier to reject any offset and/or 1/f noise present in a signal path between the modulator and a correlated double sampling integrator.

10. The apparatus of claim 7 , wherein the register is loaded with an integer value on a rising edge of a logic signal load.

11. The apparatus of claim 7 , wherein the counter is configured to count a number of chopper clock cycles after being reset.

12. The apparatus of claim 7 , wherein, when digitizing is complete, the comparator is further configured to output a logic signal to force the second switch and third switch to close, allowing the held voltage to be discharged.

13. The apparatus of claim 7 , wherein, when the Gated CDS integrator operates under a correlated double sampling integration mode, a first switch is closed and the chopped signal is toggled between a second switch and a third switch with non-overlapping intervals.

14. The apparatus of claim 13 , wherein when the chop signal is a logic 1, the third switch is closed and the second switch is open, and an output of a transconductance amplifier is equal to zero volts plus an offset voltage equal to an input voltage.

15. A Gated CDS Integrator, comprising:
a modulator preceding a linear amplifier to reject any offset or 1/f noise present in a signal path between the modulator and a correlated double sampling integrator; wherein when a counter and correlated double sampling integrator are reset, a first switch is closed and the correlated double sampling integrator is configured to demodulate a signal present at an output of the linear amplifier.

16. The Gated CDS Integrator of claim 15 , wherein the linear amplifier is between the modular and a first capacitor.

Assignees

• Nasa

Inventors

• Quilligan Gerard T
• Aslam Shahid

Classifications

• H03F2203/45288

  Differential amplifier with circuit arrangements to enhance the transconductance · CPC title

• H03F2203/45212

  the differential amplifier being designed to have a reduced offset · CPC title

• H03F2200/264

  An operational amplifier based integrator or transistor based integrator being used in an amplifying circuit · CPC title

• H03F3/387 Primary

  with semiconductor devices only · CPC title

• H03F1/26

  Modifications of amplifiers to reduce influence of noise generated by amplifying elements · CPC title