Class D amplifier circuit

Patent metadata

Field	Value
Publication number	US-9628040-B2
Application number	US-201514836006-A
Country	US
Kind code	B2
Filing date	Aug 26, 2015
Priority date	Aug 29, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

This application relates to Class D amplifier circuits ( 200 ). A modulator ( 201 ) controls a Class D output stage ( 202 ) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block ( 205 ), which may comprise an ADC ( 207 ), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input ( 204 ) of a signal selector block ( 203 ). The input signal may be received at a second input ( 206 ) of the signal selector block ( 203 ). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block ( 205 ).

First claim

The invention claimed is:

1. A Class D amplifier circuit for receiving a digital input signal and outputting an analog output signal comprising:
a class-D output stage;
a digital modulator for generating at least one control signal for controlling said class-D output stage based on a modulator input signal;
an error block for generating an error signal based on said analog output signal and said digital input signal;
a signal selector block configured to receive the error signal at a first input, receive a version of the digital input signal at a second input and generate the modulator input signal; wherein:
said signal selector block is operable in a first mode and a second mode of operation, wherein:
in the first mode the modulator input signal is based at least in part on the error signal; and
in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal; and

a signal selection controller configured to control the mode of operation of the signal selector block based on an indication of the amplitude of the digital input signal.

2. A Class D amplifier circuit as claimed in claim 1 wherein said signal selector block comprises a first signal path between said first input and a selector module and a second signal path between said second input and said selector module, wherein the selector module is configured to generate the modulator input signal based on signals from the first signal path and the second signal path.

3. A Class D amplifier circuit as claimed in claim 2 wherein said selector module is operable in a combiner state to combine the signal from the first signal path with the signal from the second signal path to provide the modulator input signal and operable in a pass-through state to provide the signal from the second signal path as the modulator input signal and wherein signal selection controller is configured to control the selector module in the combiner state in the first mode and in the pass-through state in the second mode.

4. A Class D amplifier circuit as claimed in claim 2 , wherein said selector module is configured to select either the signal from the first signal path or the signal from the second signal path to provide the modulator input signal and wherein said signal selection controller is configured to control the selector module to select the signal from the first signal path in the first mode and the signal from the second signal path in the second mode.

5. A Class D amplifier circuit as claimed in claim 2 wherein said first signal path comprises at least one variable gain element and wherein said signal selection controller is configured to control the at least one variable gain element to provide a first gain setting in the first mode and a second gain setting in the second mode.

6. A Class D amplifier circuit as claimed in claim 5 wherein said second gain setting is zero.

7. A Class D amplifier circuit as claimed in claim 5 wherein said signal selection controller is configured to control the at least one variable gain element to provide a controlled transition in gain between said first and second gain settings that involves at least one intermediate gain setting.

8. A Class D amplifier circuit as claimed in claim 5 wherein said at least one variable gain element comprises a loop filter having a variable gain.

9. A Class D amplifier circuit as claimed in claim 8 wherein the loop filter comprises an integrator and the signal selection controller is configured to control the integrator time constant of said integrator to vary the gain of the loop filter.

10. A Class D amplifier circuit as claimed in claim 2 wherein said first signal path comprises a loop filter and said signal selection controller is configured to enable the loop filter in the first mode and disable the loop filter in the second mode.

11. A Class D amplifier circuit as claimed in claim 1 wherein the error block comprises an analog to digital converter coupled to receive the output signal and wherein said signal selection controller is configured to enable the analog to digital converter in the first mode and disable the analog to digital converter in the second mode.

12. A Class D amplifier circuit as claimed in claim 1 further comprising an envelope detector for determining an envelope value for the digital input signal wherein signal selection controller is configured to use said envelope value as the indication of amplitude of the digital input signal.

13. A Class D amplifier circuit as claimed in claim 1 wherein said signal selection controller is configured to receive an indication of a volume control setting and to use said indication of a volume control setting as the indication of the amplitude of the digital input signal.

14. A Class D amplifier circuit as claimed in claim 1 wherein the signal selection controller is configured to transition from the first mode of operation to the second mode of operation if the indication of the amplitude of the digital input signal drops below a first amplitude threshold and to transition from the second mode of operation to the first mode of operation if the indication of the amplitude of the digital input signal rises above a second amplitude threshold.

15. A Class D amplifier circuit as claimed in claim 1 wherein the signal selection controller is configured to initiate any transition between the first and second modes at a time when the magnitude of the input signal is at or below a first magnitude level.

16. A Class D amplifier circuit as claimed in claim 15 comprising a low-level detector for detecting when the magnitude of the input signal is at or below the first magnitude level.

17. An electronic apparatus comprising a Class D amplifier circuit as claimed in claim 1 .

18. An electronic apparatus as claimed in claim 17 wherein said apparatus is at least one of: a portable device; a battery power device; a computing device; a communications device; a gaming device; a mobile telephone; a personal media player; a laptop, tablet or notebook computing device.

Assignees

• Cirrus Logic Int Semiconductor Ltd

Inventors

• Lesso John Paul
• Ido Toru

Classifications

• H03F2200/102

  A non-specified detector of a signal envelope being used in an amplifying circuit · CPC title

• H03F2200/432

  Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier · CPC title

• H03F3/2173

  of the bridge type · CPC title

• H03F3/187

  in integrated circuits · CPC title

• H03F1/34

  Negative-feedback-circuit arrangements with or without positive feedback (H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence {; for rejection of common mode signals H03F3/45479}) · CPC title