Methods of forming a gate contact for a semiconductor device above the active region

Patent metadata

Field	Value
Publication number	US-9899321-B1
Application number	US-201615373691-A
Country	US
Kind code	B1
Filing date	Dec 9, 2016
Priority date	Dec 9, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

One illustrative method disclosed includes, among other things, completely forming a first conductive structure comprising one of a conductive gate contact structure (CB) or a conductive source/drain contact structure (CA), wherein the entire conductive gate contact structure (CB) is positioned vertically above a portion of an active region of a transistor device, and, after completely forming the first conductive structure, completely forming a second conductive structure comprising the other of the conductive gate contact structure (CB) or the conductive source/drain contact structure (CA).

First claim

What is claimed:

1. A method of forming a conductive gate contact structure (CB) for a gate structure for a transistor device and a conductive source/drain contact structure (CA) for said transistor device, wherein said transistor device is formed above an active region of a semiconducting substrate surrounded by an isolation region, the method comprising:
completely forming a first conductive structure comprising one of said conductive gate contact structure (CB) or said conductive source/drain contact structure (CA), wherein the entire first conductive structure is positioned vertically above a portion of said active region; and
after completely forming said first conductive structure, completely forming a second conductive structure comprising the other of said conductive gate contact structure (CB) or said conductive source/drain contact structure (CA), wherein the entire second conductive structure is positioned vertically above a portion of said active region.

2. The method of claim 1 , wherein completely forming said first conductive structure comprises completely forming said conductive gate contact structure (CB) and wherein completely forming said second conductive structure comprises completely forming said conductive source/drain contact structure (CA).

3. The method of claim 1 , wherein completely forming said first conductive structure comprises completely forming said conductive source/drain contact structure (CA), wherein completely forming said second conductive structure comprises completely forming said conductive gate contact structure (CB), and wherein said conductive gate contact structure (CB) and said conductive source/drain contact structure (CA) comprise a same conductive material.

4. The method of claim 1 , wherein completely forming said first conductive structure comprises performing a first deposition process to deposit a first conductive material for said first conductive structure and performing a first planarization process to remove portions of said first conductive material so as to define said first conductive structure.

5. The method of claim 4 , wherein, after performing said first deposition process and said first planarization process, completely forming said second conductive structure comprises performing a second deposition process to deposit a second conductive material for said second conductive structure and performing a second planarization process to remove portions of said second conductive material so as to define said second conductive structure.

6. The method of claim 1 , wherein an outer perimeter of said conductive gate contact structure (CB) is surrounded by a spacer comprised of an insulating material.

7. A method of forming a conductive gate contact structure (CB) for a gate structure for a transistor device and a conductive source/drain contact structure (CA) for said transistor device, wherein said transistor device is formed above an active region of a semiconducting substrate surrounded by an isolation region, the method comprising:
performing at least one gate contact etching process through a first patterned etch mask to define a gate contact cavity that exposes a portion of said gate structure of said transistor device;
forming an internal spacer within said gate contact cavity;
forming said conductive gate contact structure (CB) within said gate contact cavity and inside said internal spacer, wherein said conductive gate contact structure (CB) is conductively coupled to said gate structure and wherein the entire conductive gate contact structure (CB) is positioned vertically above a portion of said active region;
after forming said conductive gate contact structure (CB), performing at least one source/drain contact etching process through a second patterned etch mask to define a source/drain contact cavity that exposes a portion of a recessed conductive source/drain metallization structure that is conductively coupled to a source/drain region of said transistor device; and
forming said source/drain contact structure (CA) within said source/drain contact cavity, wherein said source/drain contact structure (CA) is conductively coupled to said recessed conductive source/drain metallization structure.

8. The method of claim 7 , wherein, prior to forming said internal spacer, the method further comprises removing said first patterned etch mask.

9. The method of claim 8 , wherein, prior to forming said source/drain contact structure (CA), the method further comprises removing said second patterned etch mask.

10. The method of claim 7 , wherein, prior to forming said source/drain contact structure (CA), the method further comprises:
forming an initial conductive source/drain metallization structure that is conductively coupled to said source/drain region of said transistor device;
performing a recess etching process on said initial conductive source/drain metallization structure to thereby define said recessed conductive source/drain metallization structure, wherein said recessed conductive source/drain metallization structure has a recessed upper surface that is positioned at a level that is below an upper surface of said gate contact structure (CB); and
forming a layer of insulating material above said recessed conductive source/drain metallization structure, wherein performing said at least one source/drain contact etching process through said second patterned etch mask to define said source/drain contact cavity removes a portion of said layer of insulating material that is positioned above said recessed conductive source/drain metallization structure.

11. The method of claim 7 , wherein performing said at least one gate contact etching process through said first patterned etch mask removes a portion of a gate cap layer positioned above said gate structure and recesses a vertical height of a sidewall spacer positioned adjacent said gate structure so as to thereby define said gate contact cavity.

12. The method of claim 7 , wherein said conductive gate contact structure (CB) and said conductive source/drain contact structure (CA) comprise a same conductive material and wherein said transistor device is one of a FinFET transistor device or a planar transistor device.

13. The method of claim 10 , wherein said internal spacer surrounds said conductive gate contact structure (CB) and physically contacts a portion of said recessed conductive source/drain metallization structure.

14. A method of forming a conductive gate contact structure (CB) for a gate structure for a transistor device and a conductive source/drain contact structure (CA) for said transistor device, wherein said transistor device is formed above an active region of a semiconducting substrate surrounded by an isolation region, the method comprising:
performing at least one gate contact etching process through a first patterned etch mask to remove a portion of a gate cap layer positioned above said gate structure and to recess a vertical height of a sidewall spacer positioned adjacent said gate structure so as to thereby define a gate contact cavity that exposes a portion of said gate structure of said transistor device;
removing said first patterned etch mask;
after removing said first patterned etch mask, forming an internal spacer within said gate contact cavity;
forming said conductive gate contact structure within said gate contact cavity and inside said internal spacer, wherein said conductive gate contact structure is conductively coupled to said gate structure and wherein the entire conductive gate contact structure (CB) is positioned vertically above a portion of said active region;
after forming said conducti

Assignees

• Globalfoundries Inc

Inventors

• Park Chanro
• Xie Ruilong
• Sung Min Gyu
• Kim Hoon

Classifications

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/076

  in via holes or trenches · CPC title