Methods of forming a protection layer on a semiconductor device and the resulting device

Patent metadata

Field	Value
Publication number	US-9634115-B2
Application number	US-201414301864-A
Country	US
Kind code	B2
Filing date	Jun 11, 2014
Priority date	Jun 11, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

One illustrative method disclosed herein includes, among other things, forming a first high-k protection layer on the source/drain regions and adjacent the sidewall spacers of a transistor device, removing a sacrificial gate structure positioned between the sidewall spacers so as to thereby define a replacement gate cavity, forming a replacement gate structure in the replacement gate cavity, forming a second high-k protection layer above an upper surface of the spacers, above an upper surface of the replacement gate structure and above the first high-k protection layer, and removing portions of the second high-k protection layer positioned above the first high-k protection layer.

First claim

What is claimed:

1. A method of forming a transistor device comprised of source/drain regions and sidewall spacers, the method comprising:
forming a first high-k protection layer directly contacting said source/drain regions and said sidewall spacer;
after forming said first high-k protection layer, removing a sacrificial gate structure positioned between said sidewall spacers so as to thereby define a replacement gate cavity between said sidewall spacers;
forming a replacement gate structure in said replacement gate cavity;
recessing said replacement gate structure and said spacers to define a second cavity and expose portions of said first high-k protection layer;
forming a gate cap material layer to partially fill said second cavity; and
forming a second high-k protection layer in said second cavity above said gate cap material layer.

2. The method of claim 1 , wherein said first and second high-k protection layers are comprised of the same high-k material.

3. The method of claim 1 , wherein said sidewalls spacers are comprised of silicon nitride.

4. The method of claim 1 , wherein, prior to forming said second high-k protection layer, the method further comprises performing an HDP CVD-etching process to form said first gate cap material layer, wherein said first gate cap material layer has an as-deposited surface that defines a recess positioned above said replacement gate structure, wherein said second high-k protection layer is formed on and in contact with said as-deposited surface of said first gate cap material layer in said recess above said replacement gate structure.

5. The method of claim 4 , further comprising:
forming a second gate cap material layer on said upper surface of said second high-k protection layer; and
performing at least one CMP process to remove excess portions of said second gate cap material layer, said second high-k protection layer and said first gate cap material layer so as to thereby define a multi-layer gate cap structure positioned above said replacement gate structure, wherein said multi-layer gate cap structure is comprised of said first gate cap material layer, said second high-k protection layer positioned on said first gate cap material layer and said second gate cap material layer positioned on said second high-k protection layer.

6. The method of claim 5 , wherein said first and second gate cap material layers are comprised of silicon nitride.

7. The method of claim 1 , wherein said transistor device is one of a planar transistor device or a FinFET transistor device.

8. A method of forming a transistor device comprised of source/drain regions and sidewall spacers, the method comprising:
forming a sacrificial gate structure and a gate cap layer above a semiconducting substrate, wherein said gate cap layer is positioned above said sacrificial gate structure;
forming sidewall spacers adjacent said sacrificial gate structure;
forming a conformal first high-k protection layer directly contacting said source/drain regions, said sidewall spacers and said gate cap layer;
forming a sacrificial material layer above said first high-k protection layer, wherein said sacrificial material layer exposes said first high-k protection layer positioned above said gate cap layer and a portion, but not all, of said first high-k protection layer positioned adjacent said sidewall spacers;
removing the exposed portions of said first high-k protection layer;
forming a layer of insulating material above said first high-k protection layer and said gate cap layer;
performing at least one planarization process to remove portions of said layer of insulating material and said gate cap layer so as to thereby expose said sacrificial gate structure;
removing said sacrificial gate structure so as to thereby define a replacement gate cavity between said sidewall spacers;
forming a replacement gate structure in said replacement gate cavity;
forming a second high-k protection layer above an upper surface of said sidewall spacers, above an upper surface of said replacement gate structure and on said layer of insulating material positioned above said first high-k protection layer; and
removing portions of said second high-k protection layer positioned above said first high-k protection layer.

9. The method of claim 8 , wherein, prior to forming said second high-k protection layer, the method further comprises performing an HDP CVD-etching process to form a first gate cap material layer on said upper surface of said sidewall spacers, said upper surface of said replacement gate structure and said layer of insulating material, wherein said first gate cap material layer has an as-deposited surface that defines a recess positioned above said replacement gate structure, wherein said second high-k protection layer is formed on and in contact with said as-deposited surface of said first gate cap material layer in said recess above said replacement gate structure.

10. The method of claim 8 , further comprising:
forming a second gate cap material layer on said upper surface of said second high-k protection layer; and
performing at least one CMP process to remove excess portions of said second gate cap material layer, said second high-k protection layer and said first gate cap material layer so as to thereby define a multi-layer gate cap structure positioned above said replacement gate structure, wherein said multi-layer gate cap structure is comprised of said first gate cap material layer, said second high-k protection layer positioned on said first gate cap material layer and said second gate cap material layer positioned on said second high-k protection layer.

11. The method of claim 8 , further comprising recessing the replacement gate structure and the sidewall spacers prior to forming the second high-k protection layer.

12. A method of forming a multi-layer gate cap structure for a transistor device comprised of sidewall spacers and source/drain regions, the method comprising:
removing a sacrificial gate structure positioned between said sidewall spacers so as to thereby define a replacement gate cavity between said sidewall spacers;
forming a replacement gate structure in said replacement gate cavity;
forming a first gate cap material layer on an upper surface of said sidewall spacers and an upper surface of said replacement gate structure, wherein said first gate cap material layer has an as-deposited surface that defines a recess positioned above said replacement gate structure;
forming a high-k protection layer on and in contact with said as-deposited surface of said first gate cap material layer in said recess above said replacement gate structure, wherein a recess remains above said high-k protection layer;
forming a second gate cap material layer on an upper surface of said high-k protection layer and in said recess above said high-k protection layer; and
removing portions of said second gate cap material layer, said high-k protection layer and said first gate cap material layer positioned laterally outside of said sidewall spacers above said source/drain regions so as to thereby define a multi-layer gate cap structure positioned above said replacement gate structure, wherein said multi-layer gate cap structure is comprised of said first gate cap material layer, said high-k protection layer positioned on said first gate cap material layer and said second gate cap material layer positioned on said high-k protection layer.

13. The method of claim 12 , wherein removing said portions of said second gate cap material layer, said high-k protection layer and said first gate cap material layer comprises performing at least one CMP p

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Park Chanro
• Cai Xiuyu

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title