Semiconductor device and manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-2016268291-A1
Application number	US-201514816420-A
Country	US
Kind code	A1
Filing date	Aug 3, 2015
Priority date	Mar 13, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

According to one embodiment, a stacked body of N layers is stacked on a semiconductor substrate, steps are provided in the stacked body such that upper layers are retracted behind lower layers, N lower openings are provided in correspondence with the individual layers of the stacked body and are equal in depth, one to N upper openings are provided on one to N lower openings and are different in depth, N lower-layer contact electrodes are provided in the lower openings, and one to N upper-layer contact electrodes are provided in the upper openings.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a stacked body of N (N is an integer of 2 or more) layers stacked on a semiconductor substrate; steps provided in the stacked body such that upper layers are retracted behind lower layers; N lower openings that are provided in correspondence with the individual layers of the stacked body and are equal in depth; one to N upper openings that are provided on one to N lower openings and are different in depth; N lower-layer contact electrodes provided in the lower openings; and one to N upper-layer contact electrodes provided in the upper openings.

2 . The semiconductor device of claim 1 , wherein top surfaces of the upper contact electrodes are equal in height.

3 . The semiconductor device of claim 1 , wherein the lower-layer contact electrodes are shorter in the upper layers than in the lower layers of the stacked body.

4 . The semiconductor device of claim 1 , wherein
the upper-layer contact electrodes dig into the lower-layer contact electrodes, and depth of digging is larger in the upper layers than in the lower layers of the stacked body.

5 . The semiconductor device of claim 1 , wherein
only the lower-layer contact electrodes are provided in contacts on the upper layers of the stacked body, and the lower-layer contact electrodes and the upper-layer contact electrodes are provided in contacts on the lower layers of the stacked body.

6 . The semiconductor device of claim 1 , wherein top surfaces of the lower-layer contact electrodes are larger in area than bottom surfaces of the upper-layer contact electrodes.

7 . The semiconductor device of claim 1 , wherein the lower-layer contact electrodes are stacked only by M (M is an integer of 2 or more) layers.

8 . The semiconductor device of claim 1 , wherein depth of the lower openings is larger than height of one layer in the stacked body.

9 . The semiconductor device of claim 1 , wherein
the stacked body includes:
word lines of N layers; and
a columnar body penetrating through the word lines of N layers,
the columnar body includes:
a central body in which a channel is formable;
a tunnel insulating film formed on an outer peripheral surface of the central body;
a charge trap film formed on an outer peripheral surface of the tunnel insulating film; and
a block insulating film formed on an outer peripheral surface of the charge trap film.

10 . A semiconductor device, comprising:
a stacked body of N (N is an integer of 2 or more) layers stacked on a semiconductor substrate; steps provided in the stacked body such that upper layers are retracted behind lower layers; N openings that are provided in correspondence to the individual layers of the stacked body and are equal in depth; and N contact electrodes provided in the openings, wherein over-etching amounts in the individual layers at positions of the openings are equal.

11 . A manufacturing method of a semiconductor device, comprising:
forming first openings equal in depth in N (N is an integer of 2 or more) steps of a stepped structure; and forming second openings different in depth on the first openings.

12 . The manufacturing method of a semiconductor device of claim 11 , comprising, after the formation of the first openings and the second openings, embedding contact plugs in the first openings and the second openings.

13 . The manufacturing method of a semiconductor device of claim 12 , wherein
forming the first openings including:
forming a first insulating film uniform in film thickness on the individual steps of the stepped structure; and
forming the first openings by patterning the first insulating film.

14 . The manufacturing method of a semiconductor device of claim 13 , wherein
forming the second openings including:
embedding a sacrifice film in the first openings;
forming a second insulating film with a top surface flattened out on the sacrifice film; and
forming the second openings by patterning the second insulating film.

15 . The manufacturing method of a semiconductor device of claim 14 , wherein
after the formation of the second openings, the sacrifice film is removed and then contact plugs are embedded in the first openings and the second openings.

16 . The manufacturing method of a semiconductor device of claim 11 , comprising:
after the formation of the first openings, embedding first contact plugs in the first openings before the formation of the second openings; and after the formation of the second openings, embedding second contact plugs in the second openings.

17 . The manufacturing method of a semiconductor device of claim 16 , wherein
forming the first openings including:
forming a first insulating film uniform in film thickness on the individual steps of the stepped structure; and
forming the first openings by patterning the first insulating film.

18 . The manufacturing method of a semiconductor device of claim 17 , wherein
forming the second openings including:
embedding the first contact plugs in the first openings;
forming a second insulating film with a top surface flattened out on the first contact plugs; and
forming the second openings by patterning the second insulating film.

19 . The manufacturing method of a semiconductor device of claim 18 , wherein, after the formation of the second openings, the second contact plugs are embedded in the second openings without removing the first contact plugs.

20 . The manufacturing method of a semiconductor device of claim 11 , wherein
depths of the first openings are set such that the first openings in the Nth or lower steps protrude from the stepped structure, a conductive film is embedded in the first openings and then the conductive film is flattened out to form contact plugs equal in height of top surface in the first openings, and forming the second openings is omitted.

Assignees

• Toshiba Kk

Inventors

• Ishimura Munio

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L21/76883

  Electricity · mapped topic

• H01L21/76816

  Electricity · mapped topic