Silicon on porous silicon

Patent metadata

Field	Value
Publication number	US-10181428-B2
Application number	US-201615247725-A
Country	US
Kind code	B2
Filing date	Aug 25, 2016
Priority date	Aug 28, 2015
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

Fabricating of radio-frequency (RF) devices involves providing a field-effect transistor formed over an oxide layer formed on a semiconductor substrate and converting at least a portion of the semiconductor substrate to porous silicon.

First claim

What is claimed is:

1. A method for fabricating a radio-frequency device, the method comprising:
providing a field-effect transistor formed over an oxide layer formed on a semiconductor substrate;
applying a photoresist layer to a backside of the semiconductor substrate;
patterning the photoresist layer to create an opening; and
converting at least a portion of the backside of the semiconductor substrate exposed in the opening to porous silicon to create a backside porous silicon portion in the semiconductor substrate, the backside porous silicon portion being positioned at least partially beneath a passive device of the radio-frequency device.

2. The method of claim 1 wherein the backside porous silicon portion in the semiconductor substrate does not laterally overlap with the field-effect transistor.

3. The method of claim 1 wherein the radio-frequency device includes a passive portion and an active portion, the backside porous silicon portion being positioned at least partially underneath the passive portion.

4. The method of claim 1 wherein the backside porous silicon portion at least partially isolates the field-effect transistor from one or more other active devices of the radio-frequency device.

5. The method of claim 1 wherein the radio-frequency device is a silicon-on-insulator device.

6. The method of claim 1 further comprising thinning the semiconductor substrate prior to said converting the at least a portion of the backside of the semiconductor substrate to porous silicon, said thinning the semiconductor substrate exposing the backside of the semiconductor substrate.

7. The method of claim 1 wherein said converting the at least a portion of the backside of the semiconductor substrate to porous silicon is performed using electrochemical etching.

8. A method for fabricating a radio-frequency device, the method comprising:
providing a substrate structure including a silicon handle wafer, an oxide layer formed on a top surface of the silicon handle wafer, and an active silicon layer disposed on the oxide layer;
selectively removing, in a passive area of the substrate structure, a first portion of the oxide layer and a first portion of the active silicon layer to at least partially expose a portion of the top surface of the silicon handle wafer;
converting the exposed portion of the top surface of the silicon handle wafer to porous silicon to form a topside porous silicon portion;
forming a first radio-frequency element using a second portion of the active silicon layer in an active area of the substrate structure; and
forming a second radio-frequency element on the substrate structure, the topside porous silicon portion being disposed at least partially laterally between the first and second radio-frequency elements.

9. The method of claim 8 further comprising forming a passive device on the substrate structure over the topside porous silicon portion.

10. The method of claim 8 further comprising forming a layer of planarizing material on the topside porous silicon portion.

11. The method of claim 10 wherein the planarizing material is silicon oxide.

12. The method of claim 10 further comprising performing chemical-mechanical planarization on the layer of planarizing material.

13. The method of claim 8 wherein said converting the exposed portion of the top surface of the silicon handle wafer to porous silicon is performed using electrochemical etching.

Assignees

• Skyworks Solutions Inc

Inventors

• Mason Jerod F
• Whitefield David Scott

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P95/064

  the removal being chemical etching · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P50/613

  of Group IV materials · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title