Non-uniform spacing in transistor stacks

Patent metadata

Field	Value
Publication number	US-9806094-B2
Application number	US-201615240771-A
Country	US
Kind code	B2
Filing date	Aug 18, 2016
Priority date	Aug 21, 2015
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

Field effect transistor stacks include a first field-effect transistor having a source finger, a drain finger, and a gate finger interposed therebetween, the source finger and the drain finger of the first field-effect transistor being separated by a first drain-to-source distance, and a second field-effect transistor in a series connection with the first field-effect transistor, the second field-effect transistor having a source finger, a drain finger, and a gate finger interposed therebetween, the source finger and the drain finger of the second field-effect transistor being separated by a second drain-to-source distance that is different than the first drain-to-source distance.

First claim

What is claimed is:

1. A field-effect transistor stack comprising:
a first field-effect transistor having a source finger, a drain finger, and a gate finger interposed therebetween, the gate finger of the first field-effect transistor having a first gate width, the source finger and the drain finger of the first field-effect transistor being separated by a first drain-to-source distance, the first field-effect transistor being an end stage of the field-effect transistor stack;
a second field-effect transistor in a series connection with, and adjacent to the first field-effect transistor, the second field-effect transistor having a source finger, a drain finger, and a gate finger interposed therebetween, the gate finger of the second field-effect transistor having a second gate width that is greater than the first gate width, the source finger and the drain finger of the second field-effect transistor being separated by a second drain-to-source distance that is greater than the first drain-to-source distance; and
a third field-effect transistor in a series connection with, and adjacent to, the second field-effect transistor, the third field-effect transistor having a source finger, a drain finger, and a gate finger interposed therebetween, the gate finger of the third field-effect transistor having a third gate width that is greater than the second gate width, the source finger and the drain finger of the third field-effect transistor being separated by a third drain-to-source distance that is greater than the second drain-to-source distance.

2. The field-effect transistor stack of claim 1 wherein the end stage of the field-effect transistor stack is a front end stage of the field-effect transistor stack coupled to an antenna node of an antenna switch circuit.

3. The field-effect transistor stack of claim 1 wherein the end stage of the field-effect transistor stack is a back end stage of the field-effect transistor stack coupled to a throw node of an antenna switch circuit.

4. The field-effect transistor stack of claim 1 wherein the first, second, and third field-effect transistors are silicon-on-insulator (SOI) transistors.

5. The field-effect transistor stack of claim 1 wherein the first field-effect transistor occupies a smaller physical area than the second field-effect transistor.

6. A field-effect transistor stack comprising:
a first field-effect transistor having a first plurality of source fingers, a first plurality of corresponding drain fingers, and a first plurality of gate fingers including a gate finger disposed between each adjacent pair of source and drain fingers of the first plurality of drain fingers and the first plurality of source fingers, each of the first plurality of gate fingers having a first gate width, a respective source finger and its corresponding adjacent drain finger of the first field-effect transistor being separated by a first drain-to-source distance, the first field-effect transistor representing an end stage of the field-effect transistor stack;
a second field-effect transistor in a series connection with, and adjacent to the first field-effect transistor, the second field-effect transistor having a second plurality of source fingers, a second plurality of corresponding drain fingers, and a second plurality of gate fingers including a gate finger disposed between each adjacent pair of source and drain fingers of the second plurality of drain fingers and the second plurality of source fingers, each of the second plurality of gate fingers having a second gate width that is greater than the first gate width, a respective source finger and its corresponding adjacent drain finger of the second field-effect transistor being separated by a second drain-to-source distance that is greater than the first drain-to-source distance; and
a third field-effect transistor in a series connection with, and adjacent to, the second field-effect transistor, the third field-effect transistor having a third plurality of source fingers, a third plurality of corresponding drain fingers, and a third plurality of gate fingers including a gate finger disposed between each adjacent pair of source and drain fingers of the third plurality of drain fingers and the third plurality of source fingers, each of the third plurality of gate fingers having a third gate width that is greater than the second gate width, a respective source finger and its corresponding adjacent drain finger of the third field-effect transistor being separated by a third drain-to-source distance that is greater than the second drain-to-source distance.

7. The field-effect transistor stack of claim 6 wherein the end stage of the field-effect transistor stack is coupled to an antenna node of an antenna switch circuit.

8. The field-effect transistor stack of claim 6 wherein the end stage of the field-effect transistor stack is coupled to a throw node of an antenna switch circuit.

9. The field-effect transistor stack of claim 8 further comprising a fourth field-effect transistor in a series connection with, and adjacent to, the third field-effect transistor, the fourth field-effect transistor having a fourth plurality of source fingers, a fourth plurality of corresponding drain fingers, and a fourth plurality of gate fingers including a gate finger disposed between each adjacent pair of source and drain fingers of the fourth plurality of drain fingers and the fourth plurality of source fingers, each of the fourth plurality of gate fingers having a fourth gate width equal to the third gate width, a respective source finger and its corresponding adjacent drain finger of the fourth field-effect transistor being separated by a fourth drain-to-source distance that is equal to the third drain-to-source distance.

10. The field-effect transistor stack of claim 6 wherein the first plurality of gate fingers comprises more gate fingers than the second plurality of gate fingers.

11. The field-effect transistor stack of claim 6 wherein the first field-effect transistor has a total periphery that is greater than a total periphery of the second field-effect transistor.

12. The field-effect transistor stack of claim 6 wherein the first field-effect transistor has a first plurality of drain fingers having second level metal traces electrically coupled thereto to provide added capacitance.

13. The field-effect transistor stack of claim 6 wherein the first field-effect transistor occupies a smaller physical area than the second field-effect transistor.

14. The field-effect transistor stack of claim 6 wherein the first field-effect transistor has a physical area equal to a physical area of the second field-effect transistor.

15. A transistor stack comprising:
a plurality of field-effect transistors connected in series;
a first field-effect transistor of the plurality of field-effect transistors having a first drain-to-source spacing and a first gate width, the first field-effect transistor representing an end stage of the transistor stack;
a second field-effect transistor of the plurality of field-effect transistors connected in series with, and adjacent to, the first field-effect transistor, the second field-effect transistor having a second drain-to-source spacing that is greater than the first drain-to-source spacing and a second gate width that is greater than the first gate width; and
a third field-effect transistor of the plurality of field-effect transistors connected in series with, and adjacent to, the second field-effect transistor, the third field-effect transistor having a third drain-to-source spacing that is greater than the second drain-to-source s

Assignees

• Skyworks Solutions Inc

Inventors

• Whitefield David Scott

Classifications

• H10D84/83138

  the IGFETs characterised by having different shapes or dimensions of their gate conductors · CPC title

• H10D84/8312

  the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions · CPC title

• H01L27/088

  Electricity · mapped topic

• H01L29/41725

  Electricity · mapped topic

• H01L27/1203 Primary

  Electricity · mapped topic