Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9472301-B2
Application number	US-201514804126-A
Country	US
Kind code	B2
Filing date	Jul 20, 2015
Priority date	Feb 28, 2013
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.

First claim

The invention claimed is:

1. A method comprising:
providing a memory cell comprising a memory element comprising a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer, wherein one or both of the first conductive material layer and the second conductive material layer comprises a stack of a metal material layer and a highly doped semiconductor material layer, wherein the memory cell has a first memory state upon fabrication corresponding to a first read current; and
applying a first programming pulse to the memory cell with a first current limit, wherein the first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.

2. The method of claim 1 , further comprising applying a second programming pulse to the memory cell with a second current limit higher than the first current limit, wherein the second programming pulse programs the memory cell to a third memory state that corresponds to a third read current greater than the second read current.

3. The method of claim 2 , further comprising applying a third programming pulse to the memory cell without a current limit, wherein the third programming pulse programs the memory cell to a fourth memory state that corresponds to a fourth read current greater than the third read current.

4. The method of claim 1 , wherein the first conductive material layer comprises one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium nitride, vanadium silicon nitride, zirconium nitride, zirconium silicon nitride, hafnium nitride, hafnium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, tungsten aluminum nitride and carbon.

5. The method of claim 1 , wherein the first conductive material layer comprises highly doped n+ polysilicon, highly doped p+ polysilicon, or highly doped polycrystalline silicon-germanium alloys.

6. The method of claim 1 , wherein the second conductive material layer comprises one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium nitride, vanadium silicon nitride, zirconium nitride, zirconium silicon nitride, hafnium nitride, hafnium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, tungsten aluminum nitride and carbon.

7. The method of claim 1 , wherein the second conductive material layer comprises highly doped n+ polysilicon, highly doped p+ polysilicon, or highly doped polycrystalline silicon-germanium alloys.

8. The method of claim 1 , wherein the first dielectric material layer comprises one or more of SiO 2 , HfO 2 , SiON, HfSiON, HfSiO x , HfAl x O y Al 2 O 3 , Si 3 N 4 , ZrO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 , SrTiO 3 , VO 2 , and VSiO.

9. The method of claim 1 , wherein the second dielectric material layer comprises one or more of SiO 2 , HfO 2 , SiON, HfSiON, HfSiO x , HfAl x O y Al 2 O 3 , Si 3 N 4 , ZrO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 , SrTiO 3 , VO 2 , and VSiO.

10. A method comprising:
providing a memory cell comprising a memory element comprising a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer, wherein one or both of the first conductive material layer and the second conductive material layer comprises a stack of a metal material layer and a highly doped semiconductor material layer; and
applying voltage pulses to the memory cell to reversibly switch the memory element between a low-resistivity state and a high-resistivity state.

11. The method of claim 10 , wherein the first conductive material layer comprises one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium nitride, vanadium silicon nitride, zirconium nitride, zirconium silicon nitride, hafnium nitride, hafnium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, tungsten aluminum nitride and carbon.

12. The method of claim 10 , wherein the first conductive material layer comprises highly doped n+ polysilicon, highly doped p+ polysilicon, or highly doped polycrystalline silicon-germanium alloys.

13. The method of claim 10 , wherein the second conductive material layer comprises one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium nitride, vanadium silicon nitride, zirconium nitride, zirconium silicon nitride, hafnium nitride, hafnium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, tungsten aluminum nitride and carbon.

14. The method of claim 10 , wherein the second conductive material layer comprises highly doped n+ polysilicon, highly doped p+ polysilicon, or highly doped polycrystalline silicon-germanium alloys.

15. The method of claim 10 , wherein the first dielectric material layer comprises one or more of SiO 2 , HfO 2 , SiON, HfSiON, HfSiO x , HfAl x O y Al 2 O 3 , Si 3 N 4 , ZrO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 , SrTiO 3 , VO 2 , and VSiO.

16. The method of claim 10 , wherein the second dielectric material layer comprises one or more of SiO 2 , HfO 2 , SiON, HfSiON, HfSiO x , HfAl x O y Al 2 O 3 , Si 3 N 4 , ZrO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 , SrTiO 3 , VO 2 , and VSiO.

Assignees

• Sandisk 3D Llc
• Sandisk Technologies Llc

Inventors

• Bandyopadhyay Abhijit
• Kumar Tanmay
• Herner Scott Brad
• Petti Christopher J
• Scheuerlein Roy E

Classifications

• H10D48/381

  Multistable devices; Devices having two or more distinct operating states · CPC title

• H01L45/147

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• G11C17/165 Primary

  Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002) · CPC title