Latching current sensing amplifier for memory array

Patent metadata

Field	Value
Publication number	US-2016372164-A1
Application number	US-201514744800-A
Country	US
Kind code	A1
Filing date	Jun 19, 2015
Priority date	Jun 19, 2015
Publication date	Dec 22, 2016
Grant date	—

Abstract

A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

First claim

What is claimed:

1 . A current sense-amplifier circuit comprising a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

2 . The current sense-amplifier circuit of claim 1 , wherein the series connected transistors are a self-biased circuit.

3 . The current sense-amplifier circuit of claim 1 , wherein the first pair of series connected transistors and the second pair of series connected transistors, each includes the common-gate node, an output-drain node, an intermediate node and an input-source node.

4 . The current sense-amplifier circuit of claim 3 , wherein the output-drain node for each of the pair of series connected transistors is connected to a pair of first current sources, respectively.

5 . The current sense-amplifier circuit of claim 3 , wherein the pair of intermediate nodes for each of the pair of series are connected to a pair of sense lines.

6 . The current sense-amplifier circuit of claim 3 , wherein the input-source node for each of the pair of series is connected to a power supply.

7 . The current sense-amplifier circuit of claim 3 , wherein the common-gate node for each pair of series connected transistors is coupled together to the output-drain node in a sense operation, and separated and reconfigured in a cross-coupled arrangement in a latch mode.

8 . The current sense-amplifier circuit of claim 7 , wherein the common-gate node, when enabled by a sense signal, selectively shorts gates of the first pair of series connected transistors to gates of the second pair of series connected transistors.

9 . The current sense-amplifier circuit of claim 7 , wherein a first transistor of each pair of series connected transistors injects a first current into a bitline true (BLT) and a bitline complement (BLC).

10 . The current sense-amplifier circuit of claim 9 , wherein a second current is drawn out of the BLT and BLC from a differential memory cell by a pair of stacked transistors.

11 . The current sense-amplifier circuit of claim 10 , wherein the each of the pair of series connected transistors is connected to a common node to form self biased current sources.

12 . A circuit, comprising:
a first pair of p-type transistors (PFETs) connected in series; a second pair of PFETs connected in series; a first PFET of the first pair of PFETs and a second PFET of the second pair of PFETs are cross coupled by a common node; and a second PFET of the first pair of PFETs and a first PFET of the second pair of PFETs are cross coupled by the common node.

13 . The circuit of claim 12 , wherein the first pair of PFETs and the second pair of PFETs form a self-biased circuit.

14 . The circuit of claim 12 , wherein a true bitline (BLT) and a complementary bitline (BLC) of a differential memory cell are coupled at an intermediate node between PFETs of the first pair of PFETs and the second pair of PFETs, respectively.

15 . The circuit of claim 14 , wherein the first pair of series connected PFETs and the second pair of series connected PFETs are each coupled in series to stacked transistors which pull a differential current from the differential memory cell through the BLT and BLC to OUT_ANALOG.

16 . The circuit of claim 14 , wherein a current is injected into the differential memory cell through the BLT and the BLC from a first PFET of the first pair of PFETs and the second pair of PFETs, respectively.

17 . The circuit of claim 16 , wherein a common-gate node for each of the first pair of PFETs and the second pair of PFETs is coupled together to an output-drain node in a sense operation, and separated and reconfigured in a cross-coupled arrangement in a latch mode.

18 . The circuit of claim 17 , wherein the common-gate node, when enabled by a sense signal, will selectively short gates of the first pair of PFETs to gates of the second pair of PFETs.

19 . The circuit of claim 17 , further comprising an isolation device to isolate the first pair of series connected PFETs and the second pair of series connected PFETs from a differential memory cell.

20 . A method comprising:
injecting a first pair of currents into a true bitline (BLT) and a complement bitline (BLC) connected to a storage cell, wherein the first pair of currents is self biased; drawing a second pair of currents out of the BLT and the BLC to provide gain and a voltage output; and once initial current sensing is complete, disconnecting the self-bias and latching transistors with a common node enabled by a latching signal to form a cross-coupled latch, wherein the sensing and latching is controlled by a single digital input, and signal margining is done by differential adjustment of the second pair of currents.

Assignees

• IBM

Inventors

• Anand Darren L
• Fifield John A
• Hunt-Schroeder Eric D
• Jacunski Mark D

Classifications

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C7/065 Primary

  Differential amplifiers of latching type · CPC title

• G11C2207/063

  Current sense amplifiers · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F2200/462

  the current being sensed · CPC title