Pellicle fabrication methods and structures thereof

US10162258B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10162258-B2
Application numberUS-201615381033-A
CountryUS
Kind codeB2
Filing dateDec 15, 2016
Priority dateDec 15, 2016
Publication dateDec 25, 2018
Grant dateDec 25, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: forming a first dielectric layer over a back surface of a substrate; after forming the first dielectric layer, forming a graphene layer over a front surface of the substrate; after forming the graphene layer, patterning the first dielectric layer to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate; while using the patterned first dielectric layer as a mask, performing an etching process to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer. 2. The method of claim 1 , further comprising: prior to forming the graphene layer over the front surface of the substrate; forming a second dielectric layer over the front surface of the substrate; forming a metal layer over the second dielectric layer; and forming the graphene layer over the metal layer. 3. The method of claim 2 , further comprising: performing the etching process, wherein the etching process etches a portion of the second dielectric layer and a portion of the metal layer, thereby forming the pellicle having the pellicle membrane that includes the graphene layer. 4. The method of claim 1 , further comprising: prior to forming the graphene layer over the front surface of the substrate, forming a silicon carbide (SiC) layer over the front surface of the substrate; and forming the graphene layer over the SiC layer; wherein performing the etching process forms the pellicle having the pellicle membrane that includes the graphene layer and the SiC layer. 5. The method of claim 4 , further comprising: prior to patterning the first dielectric layer to form the opening in the first dielectric layer, forming a first protection layer over the SiC layer; and forming a second protection layer over the first protection layer. 6. The method of claim 5 , wherein the first protection layer includes at least one of an amorphous silicon layer and a nitride layer, and wherein the second protection layer includes a polymer layer. 7. The method of claim 5 , further comprising: after forming the pellicle having the pellicle membrane that includes the graphene layer and the SiC layer, removing the first protection layer and the second protection layer. 8. The method of claim 1 , further comprising: after forming the pellicle having the pellicle membrane that includes the graphene layer, forming a capping layer over the graphene layer, wherein the capping layer has a thickness equal to or less than about 10 nm. 9. The method of claim 8 , wherein the capping layer includes one or more of rhodium (Rh), ruthenium (Ru), technetium (Tc), molybdenum (Mo), niobium (Nb), zirconium (Zr), titanium (Ti), neodymium (Nd), calcium (Ca), beryllium (Be), rubidium (Rb), lanthanum (La), cerium (Ce), barium (Ba), bromine (Br), sodium (Na), selenium (Se), cesium (Cs), potassium (K), phosphorous (P), europium (Eu), praseodymium (Pr), samarium (Sm), tungsten (W), vanadium (V), hafnium (Hf), dysprosium (Dy), gadolinium (Gd), lithium (Li), boron carbide, silicon carbide, carbon, silicon nitride, silicon, and alloys or compounds thereof. 10. The method of claim 1 , wherein a transmittance of the pellicle membrane is greater than or equal to about 90%. 11. The method of claim 4 , wherein a carbon content of the SiC layer is greater than about 20%. 12. A method, comprising: forming a graphene layer over a substrate; mounting, with an adhesive, a pellicle frame to the graphene layer; and separating the graphene layer from the substrate while the pellicle frame remains mounted to the graphene layer, thereby providing a pellicle having a pellicle membrane including the graphene layer. 13. The method of claim 12 , further comprising: prior to forming the graphene layer over the substrate, forming a dielectric layer over the substrate, wherein the substrate includes a semiconductor substrate; and forming the graphene layer over the dielectric layer. 14. The method of claim 13 , further comprising: forming the dielectric layer, wherein the dielectric layer includes a nitride layer; and performing a wet etching process to separate the graphene layer from the nitride layer. 15. The method of claim 12 , further comprising: forming the graphene layer over the substrate, wherein the substrate includes a metal foil; and etching the metal foil to separate the graphene layer from the metal foil. 16. The method of claim 15 , wherein the metal foil includes at least one of a nickel (Ni) metal foil, a copper (Cu) metal foil, and a Cu—Ni metal foil. 17. The method of claim 12 , further comprising: after separating the graphene layer from the substrate, forming a capping layer over the graphene layer, wherein the capping layer has a thickness equal to or less than about 10 nm. 18. The method of claim 17 , wherein the capping layer includes one or more of rhodium (Rh), ruthenium (Ru), technetium (Tc), molybdenum (Mo), niobium (Nb), zirconium (Zr), titanium (Ti), neodymium (Nd), calcium (Ca), beryllium (Be), rubidium (Rb), lanthanum (La), cerium (Ce), barium (Ba), bromine (Br), sodium (Na), selenium (Se), cesium (Cs), potassium (K), phosphorous (P), europium (Eu), praseodymium (Pr), samarium (Sm), tungsten (W), vanadium (V), hafnium (Hf), dysprosium (Dy), gadolinium (Gd), lithium (Li), boron carbide, silicon carbide, carbon, silicon nitride, silicon, and alloys or compounds thereof. 19. A structure, comprising: an EUV lithographic mask including a patterned surface; and a pellicle mounted to the EUV lithographic mask, wherein the pellicle includes a pellicle frame and a pellicle membrane suspended by the frame a distance away from the patterned surface; wherein the pellicle includes a carbon-based pellicle membrane including one of a graphene pellicle membrane, a graphene-silicon carbide (SiC) pellicle membrane, and a SiC pellicle membrane. 20. The method of claim 18 , wherein the pellicle includes one of the graphene-SiC pellicle membrane and the SiC pellicle membrane, and wherein a carbon content of the SiC is greater than about 20%.

Assignees

Inventors

Classifications

  • characterised by the processes involved to create the masks · CPC title

  • for lift-off processes · CPC title

  • H10P76/405Primary

    characterised by their composition, e.g. multilayer masks · CPC title

  • G03F1/62Primary

    Pellicles, e.g. pellicle assemblies, e.g. having membrane on support frame; Preparation thereof · CPC title

  • Reflection masks; Preparation thereof · CPC title

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What does patent US10162258B2 cover?
A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that expo…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P76/405. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 25 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 11 related publications on this page (citations in our corpus or others sharing the same primary CPC).