Package structures and methods of forming the same

Patent metadata

Field	Value
Publication number	US-10153222-B2
Application number	US-201715712987-A
Country	US
Kind code	B2
Filing date	Sep 22, 2017
Priority date	Nov 14, 2016
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

First claim

What is claimed is:

1. A method comprising:
attaching a first die to a first side of a first component using first electrical connectors;
attaching a first side of a second die to the first side of the first component using second electrical connectors;
attaching a dummy die to the first side of the first component in a scribe line region of the first component;
adhering a cover structure to a second side of the second die; and
singulating the first component and the dummy die to form a package structure.

2. The method of claim 1 , wherein the first component is a third die.

3. The method of claim 1 further comprising:
mounting the package structure to a second substrate, the first component being interposed between the first and second dies and the second substrate.

4. The method of claim 1 , wherein singulating comprises sawing through the first component and the dummy die to form the package structure.

5. The method of claim 1 , wherein the first component is a bulk substrate including a redistribution structure, the first and second dies being attached to the redistribution structure.

6. The method of claim 1 , wherein the first die comprises one or more logic dies, and wherein the second die comprises one or more memory dies.

7. The method of claim 1 further comprising:
forming through vias extending through the first component, the first and second dies being electrically coupled to the through vias;
forming third electrical connectors on a second side of the first component, the second side being opposite the first side, the third electrical connectors being electrically coupled to the through vias;
mounting the package structure to a second substrate using the third electrical connectors; and
bonding a surface mount device (SMD) to the second substrate.

8. The method of claim 1 , wherein the dummy die and the cover structure are made of silicon.

9. A method comprising:
bonding a first die to a first side of a first structure using first electrical connectors;
bonding a memory die to the first side of the first structure using second electrical connectors, the memory die being adjacent the first die;
attaching a second die to a back side of the memory die, the second die having a thickness greater than a thickness of the memory die; and
singulating the first structure to form a package structure.

10. The method of claim 9 , wherein a thickness of the second die is greater than or equal to 120 μm.

11. The method of claim 9 , wherein attaching the second die to the back side of the memory die comprises bonding the second die to the back side of the memory die, the second die being a memory die that is electrically coupled to the memory die.

12. The method of claim 9 , wherein attaching the second die to the back side of the memory die comprises adhering the second die to the back side of the memory die with an adhesive layer, the second die being made of a bulk material and not including any active or passive devices.

13. The method of claim 9 further comprising:
forming an underfill between the first side of the first structure and the first die and the memory die and surrounding the first electrical connectors and the second electrical connectors; and
encapsulating the first die and the memory die with an encapsulant, the encapsulant adjoining portions of the underfill.

14. The method of claim 9 further comprising:
adhering a plurality of dummy dies to the first side of the first structure in scribe line regions of the first structure, wherein singulating the first structure to form the package structure comprises singulating the plurality of dummy dies.

15. The method of claim 9 further comprising:
before bonding the first die to a first side of a first structure, forming through vias in the first structure;
forming a first redistribution structure on the through vias, the first redistribution structure being the first side of the first structure, the first redistribution structure being electrically coupled to the through vias;
thinning a second side of the first structure to expose ends of the through vias, the second side being opposite the first side;
forming a second redistribution structure on the second side of the first structure thereby forming a first interposer, the second redistribution structure being electrically coupled to the exposed ends of the through vias;
forming third electrical connectors on and electrically coupled to the first redistribution structure;
bonding the third electrical connectors to a first substrate; and
bonding a surface mount device (SMD) to the first substrate adjacent one of the third electrical connectors.

16. The method of claim 9 , wherein the first die comprises one or more logic dies.

17. A method comprising:
bonding a first die to a first side of a first substrate using first electrical connectors;
bonding a first side of a second die to the first side of the first substrate using second electrical connectors;
attaching a dummy structure to the first side of the first substrate in a scribe line region of the first substrate;
adhering a cover structure to a second side of the second die, the second side being opposite the first side;
singulating the first substrate and the dummy structure to form a package structure; and
mounting the package structure to a second substrate, the first substrate being interposed between the first and second dies and the second substrate.

18. The method of claim 17 , wherein the dummy structure is made of silicon.

19. The method of claim 17 , wherein the second die comprises one or more memory dies, the cover structure being thicker than each of the one or more memory dies.

20. The method of claim 17 , wherein the cover structure is further adhered to a back side of the first die and to a top surface of the dummy structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Hu Hsien-Pin
• Lin Jing-Cheng
• Lu Szu-Wei
• Hou Shang-Yun
• Wei Wen-Hsin
• Shih Ying-Ching
• Wu Chi-Hsi

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title