Semiconductor packages and methods of packaging semiconductor devices

Patent metadata

Field	Value
Publication number	US-2015357256-A1
Application number	US-201514731484-A
Country	US
Kind code	A1
Filing date	Jun 5, 2015
Priority date	Jun 8, 2014
Publication date	Dec 10, 2015
Grant date	—

Abstract

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

First claim

What is claimed is:

1 . A method for forming a semiconductor package comprising:
providing a wafer having first and second major surfaces, wherein the wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer, and processing the wafer, wherein processing the wafer comprises
separating the wafer into a plurality of individual dies, wherein an individual die comprises first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die, and
forming an encapsulant material, wherein the encapsulant material covers at least a portion of the first and second sidewalls of the die.

2 . The method of claim 1 wherein processing the wafer comprises:
performing a first singulation process which comprises a full cut to separate the wafer into the plurality of individual dies, wherein adjacent dies are separated by a gap; and
increasing the gap between adjacent dies.

3 . The method of claim 2 wherein:
forming the encapsulant material comprises providing encapsulant material which at least fills and covers the gaps between adjacent dies; and
processing the wafer further comprises performing a second singulation process through the encapsulant material which fills the gaps such that the encapsulant material covers at least a portion of the first and second sidewalls of the die.

4 . The method of claim 3 wherein processing the wafer comprises forming a backside protective layer, wherein the backside protective layer is formed over the second major surface of the dies.

5 . The method of claim 3 wherein processing the wafer comprises:
providing a temporary support having top and bottom surfaces;
providing an adhesive layer over the top surface of the temporary support; and
attaching the individual dies to the adhesive layer, wherein the external electrical contacts are at least partially embedded in the adhesive layer.

6 . The method of claim 5 wherein processing the wafer comprises removing at least a portion of the encapsulant material over the second surface of the dies.

7 . The method of claim 3 wherein forming the encapsulant material comprises:
providing a stencil over the first surface of the dies, wherein the stencil covers the first surface of the dies and comprises openings which expose the gaps between adjacent dies; and
the encapsulant material is provided by dispensing the encapsulant material to fill and cover the gaps.

8 . The method of claim 2 wherein forming the encapsulant material comprises jetting or spraying the encapsulant along edges of the dies, wherein the encapsulant material conforms to sidewalls of the dies.

9 . The method of claim 1 wherein processing the wafer comprises:
providing an encapsulant layer over one of the first or second major surface of the wafer;
performing the first singulation process after providing the encapsulant layer to separate the wafer into the plurality of individual dies having the encapsulant layer over one of the first or second major surface of the dies; and
performing a treatment process to transform the encapsulant layer into liquid phase to form the encapsulant material which covers at least a portion of the first and second sidewalls of the die.

10 . The method of claim 1 wherein processing the wafer comprises:
providing at least a first encapsulant layer which covers at least the first major surface of the wafer and partially covers the external electrical contacts;
performing a first singulation process after providing the first encapsulant layer to separate the wafer into the plurality of individual dies having the first encapsulant layer at least over the first major surface of the dies, wherein adjacent dies are separated by a gap; and
performing a second singulation process through the gaps such that the encapsulant material is formed to cover at least a portion of the first and second sidewalls of the die.

11 . The method of claim 10 wherein processing the wafer comprises:
performing a treatment process to transform the encapsulant layer into liquid phase to at least fills the gaps between adjacent dies.

12 . The method of claim 10 wherein processing the wafer comprises:
forming grooves through first major surface of the wafer, wherein the grooves extend from the first major surface of the wafer and partially into the wafer; and wherein
the first and second sidewalls of the dies comprise a step profile after performing the first singulation process.

13 . The method of claim 12 wherein processing the wafer comprises:
providing a second encapsulant layer which covers the first encapsulant layer and fills the gaps between adjacent dies; and wherein
the second singulation process is performed after providing the second encapsulant layer such that the encapsulant material is formed by the first and second encapsulant layers which cover at least a portion of the first and second sidewalls of the die.

14 . The method of claim 1 wherein processing the wafer comprises:
providing at least a first encapsulant layer which covers at least the first major surface of the wafer and at least partially covers the external electrical contacts; and
forming first type grooves through the first major surface of the wafer, wherein the first type grooves extend from the first major surface of the wafer and partially into the wafer.

15 . The method of claim 14 wherein the first encapsulant layer also fills the first type grooves and processing the wafer comprises:
forming second type grooves through the first type grooves filled with the first encapsulant layer, wherein the second type grooves comprise a depth deeper than the first type grooves; and
removing a portion of the wafer from the second major surface of the wafer.

16 . The method of claim 14 wherein processing the wafer comprises providing a second encapsulant layer which covers the first encapsulant layer and fills the first type grooves.

17 . The method of claim 1 wherein processing the wafer comprises:
performing a first singulation process which comprises a full cut to separate the wafer into the plurality of individual dies, wherein adjacent dies are separated by a gap; and wherein
forming the encapsulant material comprises providing an encapsulant layer which covers the external electrical contacts and the first surface of the dies and fills the gaps between adjacent dies, and patterning the encapsulant layer to form the encapsulant material which covers at least a portion of the first and second sidewalls of the die.

18 . The method of claim 1 wherein processing the wafer comprises:
performing a first singulation process which comprises a full cut to separate the wafer into the plurality of individual dies;
providing a support structure, wherein the support structure comprises at least one recess; and wherein
forming the encapsulant material comprises filling the at least recess with the encapsulant material such that the encapsulant material covers at least a portion of the first and second sidewalls of the die.

19 . A method for forming a semiconductor package comprising:
providing a semiconductor die, wherein the die comprises first and second major surfaces and first and second sidewalls, and external electrical contacts formed on the first major surface of the die; and forming an encapsulant material, wherein the encapsulant material covers at least a portion of the first

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Suthiwongsunthorn Nathapong
• Dimaano Antonio Jr Bambalan
• Huang Rui
• Tan Hua Hong
• Le Kriangsak Sae
• Ho Beng Yeung
• De Vera Nelson Agbisit
• Robles Roel Adeva
• Micla Wedanni Linsangan

Classifications

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W46/301

  for alignment · CPC title