Gate-all-around fin device

Patent metadata

Field	Value
Publication number	US-10147822-B2
Application number	US-201715474055-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Nov 19, 2014
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

First claim

What is claimed:

1. A structure comprising:
a substrate of a first conductivity type;
a first doped well located in the substrate;
a doped well ring of a second conductivity type located in the substrate adjacent to the first doped well and enclosing a central doped well of the first conductivity type;
a first doped fin of the first conductivity type located over a first portion of the central doped well;
a second doped fin of the second conductivity type located over a second portion of the doped well ring;
a gate structure located adjacent to the first doped fin partially over the doped well ring and partially over the central doped well; and
a source contact located over the first doped fin,
wherein the source contact includes alternating p regions and n regions.

2. The structure of claim 1 , wherein the gate structure is in a dielectric fill material.

3. The structure of claim 1 , wherein the first doped well is of the first conductivity type.

4. The structure of claim 3 , wherein:
the doped well ring is a shallow N-well and the first doped well and the central doped well are P-wells; and
the gate structure is formed partially over the shallow N-well and partially over the central doped well.

5. The structure of claim 1 , wherein the gate structure is a wraparound gate structure which wraps around the first doped fin.

6. The structure of claim 5 , further comprising a drain contact formed over the second doped fin.

7. The structure of claim 6 , wherein the drain contact is an N-doped region.

8. The structure of claim 1 , wherein the first doped well surrounds the doped well ring.

9. The structure of claim 8 , wherein the gate structure is located between the first doped fin and the second doped fin.

10. The structure of claim 2 , further comprising a deep P-type implant region formed in the substrate beneath the first doped well, the doped well ring and the central doped well, wherein the doped well ring and the central doped well extend from the dielectric fill material to the deep P-type implant region, and the doped well ring completely surrounds sidewalls of the central doped well.

Assignees

• IBM

Inventors

• Campi Jr John B
• Gauthier Jr Robert J
• Mishra Rahul
• Mitra Souvick
• Muhammad Mujahid

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01G4/20

  using combinations of dielectrics from more than one of groups H01G4/02 - H01G4/06 (H01G4/12 takes precedence) · CPC title

• H01G4/206

  inorganic and synthetic material · CPC title