Semiconductor device and a method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9947657-B2
Application number	US-201615090202-A
Country	US
Kind code	B2
Filing date	Apr 4, 2016
Priority date	Jan 29, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.

First claim

What is claimed is:

1. A semiconductor device including a fin field effect transistor, comprising:
a first gate electrode disposed between gate sidewall spacers made of an insulating material;
a first source/drain (S/D) region disposed adjacent to the first gate electrode;
a first S/D contact made of a conductive material and disposed on the first S/D region, the S/D contact being not in direct contact with the first gate electrode;
a first spacer layer made of an insulating material and disposed between one of the gate sidewall spacers and the first S/D contact;
a first contact layer made of a conductive material and being in direct contact with the first gate electrode and an uppermost portion and a side face of the first S/D contact; and
a first wiring layer integrally formed with the first contact layer, wherein:
there is no interface between the first contact layer and the first wiring layer in a cross sectional view, and
the first contact layer has a smaller area than the first wiring layer in plan view.

2. The semiconductor device of claim 1 , further comprising a first gate cap insulating layer formed over the first gate electrode,
wherein a side surface of the first contact layer is in contact with the first gate cap insulating layer.

3. The semiconductor device of claim 1 ,
wherein a bottom surface of the first contact layer is in contact with an upper surface of the first spacer layer and an upper surface of the one of the gate sidewall spacers.

4. The semiconductor device of claim 2 , further comprising a first interlayer dielectric layer disposed over at least the first cap insulating layer, wherein:
the first wiring layer is embedded in an upper portion of the first interlayer dielectric layer, and
the first contact layer penetrates a bottom portion of the first interlayer dielectric layer and the first gate cap insulating layer.

5. The semiconductor device of claim 4 , further comprising:
a second gate electrode;
a gate contact plug made of a conductive material and being disposed on the second gate electrode;
a second contact layer made of a conductive material and being in contact with the gate contact plug; and
a second wiring layer integrally formed with the second contact layer, wherein:
there is no interface between the second contact layer and the second wiring layer in a cross sectional view,
the second wiring layer is embedded in the upper portion of the first interlayer dielectric layer, and
the second contact layer penetrates the bottom portion of the first interlayer dielectric layer and a second gate cap insulating layer.

6. The semiconductor device of claim 5 , further comprising:
a second S/D region;
a second S/D contact disposed on the second S/D region;
a third contact layer made of a material and being in contact with the second S/D contact; and
a third wiring layer integrally formed with the third contact layer, wherein:
there is no interface between the third contact layer and the third wiring layer in a cross sectional view,
the third wiring layer is embedded in the upper portion of the first interlayer dielectric layer, and
the third contact layer penetrates the bottom portion of the first interlayer dielectric layer.

7. The semiconductor device of claim 6 , further comprising a fin structure, wherein:
the first contact layer and the third contact layer are disposed over the fin structure in plan view, and
the second contact layer is not disposed over the fin structure in plan view.

8. The semiconductor device of claim 6 , wherein upper surfaces of the first S/D contact, the second S/D contact and the gate contact plug are located substantially at a same plane.

9. The semiconductor device of claim 1 , wherein:
the first S/D contact includes at least one conductive material selected the group consisting of Co, Ni, W and Mo, and
the first contact layer includes at least one conductive material selected the group consisting of TiN, Ti, Cu and Al.

10. A semiconductor device including a fin field effect transistor, comprising:
a first gate electrode disposed between gate sidewall spacers made of an insulating material;
a first gate contact layer made of a first conductive material and being disposed on the first gate electrode;
a first source/drain (S/D) region disposed adjacent to the first gate electrode;
a first S/D contact made of a conductive material and being disposed on the first S/D region, the S/D contact being not in direct contact with the first gate electrode;
a first spacer layer made of an insulating material and disposed between one of the gate sidewall spacers and the first S/D contact;
a first contact layer made of a conductive material and being in direct contact with an uppermost portion of the first gate contact layer and an uppermost portion of the first S/D contact;
a first interlayer dielectric layer disposed over the first gate contact layer and the first S/D contact; and
a first wiring layer integrally formed with the first contact layer, wherein:
there is no interface between the first contact layer and the first wiring layer in a cross sectional view,
the first contact layer has a smaller area than the first wiring layer in plan view,
the first wiring layer is embedded in an upper portion of the first interlayer dielectric layer,
the first contact layer penetrates a bottom portion of the first interlayer dielectric layer,
the first wiring layer protrudes.

11. The semiconductor device of claim 10 ,
wherein a bottom surface of the first contact layer is in contact with an upper surface of the first spacer layer and an upper surface of the one of the gate sidewall spacers.

12. The semiconductor device of claim 10 , further comprising:
a second gate electrode;
a second gate contact layer disposed on the second gate electrode;
a second contact layer made of a conductive material and being in contact with the second gate contact layer; and
a second wiring layer integrally formed with the second contact layer, wherein:
there is no interface between the second contact layer and the second wiring layer in a cross sectional view,
the second wiring layer is embedded in the upper portion of the first interlayer dielectric layer, and
the second contact layer penetrates the bottom portion of the first interlayer dielectric layer.

13. The semiconductor device of claim 12 , further comprising:
a second S/D region;
a second S/D contact made of a conductive material and being disposed on the second S/D region;
a third contact layer made of a conductive material and being in contact with the second S/D contact; and
a third wiring layer integrally formed with the third contact layer, wherein:
there is no interface between the third contact layer and the third wiring layer in a cross sectional view,
the third wiring layer is embedded in the upper portion of the first interlayer dielectric layer, and
the third contact layer penetrates the bottom portion of the first interlayer dielectric layer.

14. The semiconductor device of claim 13 , further comprising a fin structure, wherein:
the third contact layer is disposed over the fin structure in plan view, and
the first and second contact layers are not disposed over the fin structure in plan view.

15. The semiconductor device of claim 13 , wherein upper surfaces of the first S/D contact, the second S/D contact and the gate contact layer are located substantially at a same plane.

16. The semiconductor device of claim 13 , wherein bottom surfaces of the first contact layer, the second contact layer and the third c

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Fang
• Liaw Jhon Jhy
• Liang Min-Chang

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title