Gate-all-around fin device

Patent metadata

Field	Value
Publication number	US-10090301-B2
Application number	US-201715441353-A
Country	US
Kind code	B2
Filing date	Feb 24, 2017
Priority date	Nov 19, 2014
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

First claim

What is claimed:

1. A method comprising:
forming a plurality of fin structures from a substrate;
forming a continuous shallow N-well in the substrate;
forming a P-well within the substrate and corresponding fin structures of the plurality of fin structures;
forming a source contact on an exposed portion of a first fin structure;
forming a drain contact on an exposed portion of an adjacent fin structure to the first fin structure; and
forming a gate structure in a dielectric fill material about the first fin structure and extending over the continuous shallow N well, wherein:
the gate structure and the first fin structure comprising the source contact are formed completely over the shallow N-well, thereby forming a floating contact.

2. The method of claim 1 , wherein the source contact and the drain contacts are formed by an epitaxial growth process followed by an n+ implantation process.

3. The method of claim 1 , wherein the dielectric fill material extends between the first fin structure and the adjacent fin structures.

4. The method of claim 3 , wherein the dielectric fill material overlaps a portion of an upper surface of the continuous shallow N-well.

5. The method of claim 4 , wherein the dielectric fill material overlaps a portion of an upper surface of the P-well.

6. The method of claim 1 , wherein the forming of the plurality of fin structures includes forming body contact fins.

7. The method of claim 1 , wherein the adjacent fin structures and the drain contacts are formed over the shallow N-type well.

8. The method of claim 1 , wherein the shallow N-type well is formed with a mask having different openings corresponding to the shallow N-type well and an ion implantation process.

Assignees

• IBM

Inventors

• Campi Jr John B
• Gauthier Jr Robert J
• Mishra Rahul
• Mitra Souvick
• Muhammad Mujahid

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01G4/206

  inorganic and synthetic material · CPC title

• H01G4/20

  using combinations of dielectrics from more than one of groups H01G4/02 - H01G4/06 (H01G4/12 takes precedence) · CPC title